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| datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933
datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 datasheet preliminary specification 1/3" color cmos 4 megapixel (2688 x 1520) image sensor with improved omnibsi-2? technology OV4689 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 00 copyright ?2013 omnivision technologies, inc. all rights reserved. this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any wa rranty otherwise arising out of any proposal, specification, or sample. omnivision technologies, inc. and all its af filiates disclaim all liab ility, including liability for infringement of any propri etary rights, relating to the use of information in this document. no license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. the information contained in this doc ument is considered proprietary to om nivision technologies, inc. and all its affiliates. this information may be dist ributed to individuals or organizations authorized by omnivision technologies, inc. to receive said information. individuals and/or organizat ions are not allowed to re-distribute said information. trademark information omnivision and the omnivision logo are registered trademarks of omnivision technologies, inc. omnibsi-2 and csp5 are trademarks of omnivision technologies, inc. all other trademarks used herein are the property of their respective owners. to learn more about omnivision te chnologies, visit www.ovt.com. omnivision technologies is publicly traded on nasdaq under the symbol ovti. color cmos 4 megapixel (2688 x 1520) image sensor with omnibsi-2? technology datasheet (csp5) preliminary specification version 1.3 october 2013 10.23.2013 preliminary specification propr ietary to omnivision technologies i ordering information ? ov04689-h67a (color, lead-free) 67-pin csp5 00 applications ? ip cameras ? sports cameras ? automotive 00 features ? automatic black level calibration (ablc) ? programmable controls for frame rate, mirror and flip, cropping, and windowing ? static defective pixel canceling ? supports output formats: 10-bit raw rgb (mipi) ? supports horizontal and vertical subsampling ? supports images sizes: 4mpixel, 3mpixel, eis1080p, 1080p, eis720p ? fast mode switching ? support 2x2 binning, 4x4 bi nning, re-sampling filter ? standard serial sccb interface ? up to 4-lane mipi serial output interface ? embedded 4k bits one-time programmable (otp) memory for part identification, etc (see sidebar note ) ? two on-chip phase lock loops (plls) ? programmable i/o drive capability ? built-in temperature sensor note only1.5k bits of otp is available for customer's use. 00 key specifications (typical) ? active array size: 2688 x 1520 ? power supply: core: 1.1 ~ 1.3v analog: 2.6 ~ 3.0v i/o: 1.7 ~ 3.0v ? power requirements: active: 163 ma (261 mw) standby: 1 ma xshutdown: <10 a ? temperature range: operating: -30c to +85c junction temperature (see table 7-2 ) stable image: 0c to +60c junction temperature (see table 7-2 ) ? output formats: 10-bit raw ? lens size: 1/3" ? input clock frequency: 6~64 mhz ? lens chief ray angle: 0 ? max s/n ratio: 38.3 db ? dynamic range: 64.6 db @ 1x gain ? maximum image transfer rate: 2688x1520: 90 fps (see table 2-1 ) 1280x720: 180 fps (see table 2-1 ) 1920x1080: 120 fps (see table 2-1 ) 672x380: 330 fps (see table 2-1 ) ? sensitivity: 1900 mv/lux-sec ? scan mode: progressive ? maximum exposure interval: 1548 t row ? pixel size: 2 m x 2 m ? dark current: 4mv/sec @ 60c junction temperature ? image area: 5440 m x 3072 m ? package dimensions: 6630 m x 5830 m note higher junction temperature degrades image quality color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies iii 00 table of contents 1 signal descriptions 1-1 2 system level description 2-1 2.1 overview 2-1 2.2 architecture 2-1 2.3 format and frame 2-4 2.4 i/o control 2-5 2.5 mipi interface 2-5 2.6 power management 2-6 2.6.1 power up sequence 2-6 2.6.2 power down sequence 2-9 2.7 reset 2-13 2.7.1 power on reset 2-13 2.7.2 software reset 2-13 2.8 hardware and software standby 2-14 2.8.1 hardware standby 2-14 2.8.2 software standby 2-14 2.9 system clock control 2-15 2.9.1 pll1 2-15 2.9.2 pll2 2-15 2.10 serial camera contro l bus (sccb) interface 2-19 2.10.1 data transfer protocol 2-19 2.10.2 message format 2-19 2.10.3 read / write operation 2-20 2.10.4 sccb timing 2-23 2.11 group write 2-24 2.12 hold 2-25 2.13 launch 2-25 2.13.1 launch mode 1 - quick manual launch 2-25 2.13.2 launch mode 2 - delay manual launch 2-26 2.13.3 launch mode 3 - quick auto launch 2-26 2.13.4 launch mode 4: delay auto launch 2-26 2.13.5 launch mode 5: repeat launch 2-26 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3 block level description 3-1 3.1 pixel array structure 3-1 3.2 subsampling 3-2 3.3 analog amplifier 3-3 3.4 10-bit a/d converters 3-3 4 image sensor core digital functions 4-1 4.1 mirror and flip 4-1 4.2 image cropping and windowing 4-2 4.3 test pattern 4-4 4.3.1 color bar 4-4 4.3.2 square 4-4 4.3.3 random data 4-5 4.3.4 transparent effect 4-5 4.3.5 rolling bar effect 4-5 4.4 gain and exposure control 4-7 4.5 high dynamic range (hdr) mode 4-9 4.5.1 sequential hdr 4-9 4.5.2 staggered hdr 4-10 4.5.3 average luminance (yavg) 4-11 4.5.4 black level calibration (blc) 4-13 4.6 one time programmable (otp) memory 4-14 4.6.1 otp other functions 4-14 4.7 temperature sensor 4-15 4.8 strobe flash and frame exposure 4-16 4.8.1 strobe flash control 4-16 4.8.2 frame exposure (frex) mode 4-19 5 image sensor processo r digital functions 5-1 5.1 dsp top 5-1 5.2 dsp_pre 5-3 5.3 otp for cluster cancellation 5-5 5.4 window control (winc) 5-6 5.5 manual white balance (mwb) 5-7 5.6 avg 5-8 10.23.2013 preliminary specification propr ietary to omnivision technologies v 6 register tables 6-1 6.1 pll control [0x0300 ~ 0x031f] 6-1 6.2 system control (sc) [0x0100 ~ 0x303f] 6-3 6.3 sccb control [0x3100 ~ 0x3106] 6-8 6.4 group hold [0x3200 ~ 0x320f] 6-9 6.5 asram control [0x3300 ~ 0x3318] 6-10 6.6 adc and analog control [0x3600 ~ 0x364c] 6-10 6.7 sensor control [0x3700 ~ 0x379a] 6-10 6.8 frex control [0x37c5 ~ 0x37df] 6-11 6.9 timing control [0x3800 ~ 0x3847] 6-13 6.10 strobe [0x3b00 ~ 0x3b05] 6-17 6.11 psram control [0x3f00 ~ 0x3f0a] 6-17 6.12 adc sync control [0x4500 ~ 0x4503] 6-18 6.13 test mode [0x8000 ~ 0x8008] 6-18 6.14 otp control [0x3d80 ~ 0x3d8d] 6-19 6.15 frame control [0x4200 ~ 0x4203] 6-20 6.16 ispfc [0x4240 ~ 0x4243] 6-21 6.17 format clip [0x4302 ~ 0x4307] 6-21 6.18 vfifo [0x4600 ~ 0x4603] 6-22 6.19 mipi top [0x4800 ~ 0x484f] 6-22 6.20 temperature monitor [04d00x ~ 0x4d23] 6-31 6.21 aec pk [0x3500 ~ 0x352b] 6-31 6.22 blc [0x4000 ~ 0x4033] 6-36 6.23 isp top [0x5000 ~ 0x5033] 6-39 6.24 pre_isp control [0x5040 ~ 0x506c] 6-42 6.25 binning control [0x5301 ~ 0x530f] 6-43 6.26 otp_dpc control [0x5000 ~ 0x552a] 6-44 6.27 windowing (win) control [0x5980 ~ 0x598c] 6-45 6.28 average (avg) control [0x5680 ~ 0x5693] 6-46 7 operating specifications 7-1 7.1 absolute maximum ratings 7-1 7.2 functional temperature 7-1 7.3 dc characteristics 7-2 7.4 timing characteristics 7-3 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8 mechanical specifications 8-1 8.1 physical specifications 8-1 8.2 ir reflow specifications 8-2 9 optical specifications 9-1 9.1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies vii 00 list of figures figure 1-1 pin diagram 1-5 figure 2-1 OV4689 block diagram 2-2 figure 2-2 reference schematic 2-3 figure 2-3 power up sequence (case 1) 2-7 figure 2-4 power up sequence (case 2) 2-8 figure 2-5 software st andby sequence 2-11 figure 2-6 power down sequence (case 1) 2-12 figure 2-7 power down sequence (case 2) 2-13 figure 2-8 pll structure 2-15 figure 2-9 message type 2-19 figure 2-10 sccb single read from random location 2-20 figure 2-11 sccb single read from current location 2-20 figure 2-12 sccb sequential re ad from random location 2-21 figure 2-13 sccb sequential re ad from current location 2-21 figure 2-14 sccb single write to random location 2-22 figure 2-15 sccb sequential wr ite to random location 2-22 figure 2-16 sccb interface timing 2-23 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 example of 2x2 binning 3-2 figure 3-3 example of 4x4 binning 3-2 figure 4-1 mirror and flip samples 4-1 figure 4-2 image croppi ng and windowing 4-2 figure 4-3 color bar types 4-4 figure 4-4 color, black an d white square bars 4-4 figure 4-5 transparent effect 4-5 figure 4-6 rolling bar effect 4-5 figure 4-7 sequential hdr mode 4-9 figure 4-8 staggered hdr wi th virtual channel 4-10 figure 4-9 staggered hdr wi thout virtual channel 4-10 figure 4-10 average-based window definition 4-11 figure 4-11 xenon flash mode 4-16 figure 4-12 led 1/ led 2 single frame mode 4-17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-13 led1/led2 mu lti-frame mode 4-17 figure 4-14 led 3 mode 4-18 figure 4-15 led 4 mode 4-18 figure 4-16 frex mode 1 4-19 figure 4-17 frex mode 2 4-19 figure 4-18 frex mode 1 timing diagram 4-20 figure 4-19 frex mode 2 (shutter delay = 0) timing diagram 4-20 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram 4-21 figure 8-1 package specifications 8-1 figure 8-2 ir reflow ramp rate requirements 8-2 figure 9-1 sensor array center 9-1 10.23.2013 preliminary specification propr ietary to omnivision technologies ix 00 list of tables table 1-1 signal descriptions 1-1 table 1-2 configuration under various conditions 1-3 table 1-3 pad symbo l and equivalent circuit 1-5 table 2-1 non hdr mode frame rate 2-4 table 2-2 staggered hdr mode frame rate 2-4 table 2-3 i/o control registers 2-5 table 2-4 power up sequence 2-6 table 2-5 power up se quence timing constraints 2-6 table 2-6 power down sequence 2-9 table 2-7 power down se quence timing constraints 2-10 table 2-8 hardware and standby description 2-14 table 2-9 pll speed limitation 2-15 table 2-10 pll registers 2-16 table 2-11 sample pll configuration 2-18 table 2-12 sccb interfa ce timing specifications 2-23 table 2-13 context switching control 2-24 table 3-1 binning-related registers 3-3 table 4-1 mirror and flip registers 4-1 table 4-2 image cropping and windowing control functions 4-2 table 4-3 test pattern registers 4-6 table 4-4 gain/exposure control registers 4-7 table 4-5 timing control 4-9 table 4-6 timing control 4-9 table 4-7 timing control 4-10 table 4-8 avg registers 4-11 table 4-9 blc registers 4-13 table 4-10 otp control registers 4-14 table 4-11 temperature sensor functions 4-15 table 4-12 frex strobe control registers 4-22 table 5-1 dsp top registers 5-1 table 5-2 pre_isp registers 5-3 table 5-3 otp for clus ter cancellation registers 5-5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 5-4 winc registers 5-6 table 5-5 mwb registers 5-7 table 5-6 avg control registers 5-8 table 6-1 pll registers 6-1 table 6-2 sc registers 6-3 table 6-3 sccb registers 6-8 table 6-4 group hold registers 6-9 table 6-5 asram control registers 6-10 table 6-6 adc and analog control registers 6-10 table 6-7 sensor control registers 6-10 table 6-8 frex control registers 6-11 table 6-9 timing control registers 6-13 table 6-10 strobe control registers 6-17 table 6-11 psram control registers 6-17 table 6-12 adc sync control registers 6-18 table 6-13 test mode registers 6-18 table 6-14 otp control registers 6-19 table 6-15 frame control registers 6-20 table 6-16 ispfc registers 6-21 table 6-17 format clip registers 6-21 table 6-18 vfifo registers 6-22 table 6-19 mipi top registers 6-22 table 6-20 temperature monitor registers 6-31 table 6-21 aec/agc registers 6-31 table 6-22 blc registers 6-36 table 6-23 isp top registers 6-39 table 6-24 pre_isp control registers 6-42 table 6-25 binning control registers 6-43 table 6-26 otp_dpc control registers 6-44 table 6-27 win control registers 6-45 table 6-28 avg control registers 6-46 table 7-1 absolute maximum ratings 7-1 table 7-2 functional temperature 7-1 table 7-3 dc characteristics (-30c < tj < 85c) 7-2 table 7-4 timing characteristics 7-3 10.23.2013 preliminary specification propr ietary to omnivision technologies xi table 8-1 package dimensions 8-1 table 8-2 reflow conditions 8-2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-1 1 signal descriptions table 1-1 lists the signal descripti ons and their corresponding pin numbers fo r the OV4689 image sensor. the package information is shown in section 8 . table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description a1 nc ? no connect a2 dvdd power power for digital circuit a3 avdd power power for analog circuit a4 dovdd power power for i/o circuit a5 atest0 reference analog reference test output a6 dvdd power power for digital circuit a7 il_pwm i/o no connect in system a8 avdd power power for analog circuit a9 nc ? no connect b1 agnd ground ground for analog circuit b2 dognd ground ground for digital circuit b3 dognd ground ground for digital circuit b4 avdd power power for analog circuit b5 xshutdown input reset and power down (active low with internal pull down resistor) b6 dognd ground ground for digital circuit b7 pvdd power power for analog circuit b8 dvdd power power for digital circuit b9 dvdd power power for digital circuit c1 avdd power power for analog circuit c2 vh reference internal analog reference c3 vn reference internal analog reference c4 dvdd power power for digital circuit c5 pwdnb input power down (active low with internal pull up resistor) c6 nc ? no connect c7 gpio i/o general purpose input/output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 c8 agnd ground ground for analog circuit c9 dognd ground ground for digital circuit d1 nc ? no connect d9 nc ? no connect e1 dvdd power power for digital circuit e9 frex i/o frame exposure control f1 dognd ground ground for digital circuit f2 mdp0 i/o mipi tx data lane 0 positive output f3 mdn0 i/o mipi tx data lane 0 negative output f4 mdp1 i/o mipi tx data lane 1 positive output f5 mdn1 i/o mipi tx data lane 1 negative output f6 dovdd power power for i/o circuit f7 strobe i/o strobe control f8 tm input test mode (active high with internal pull down resistor) f9 fsin i/o frame sync i/o g1 agnd ground ground for analog circuit g2 mdp2 i/o mipi tx data lane 2 positive output g3 evdd power power for mipi circuit (connect to dvdd) g4 evdd power power for mipi circuit (connect to dvdd) g5 egnd ground ground for mipi circuit g6 sioc input sccb input clock g7 dovdd power power for i/o circuit g8 href i/o href output g9 dognd ground ground for digital circuit h1 avdd power power for analog circuit h2 mdn2 i/o mipi tx data lane 2 negative output h3 egnd ground ground for mipi circuit h4 mcp i/o mipi tx clock lane positive output h5 mdn3 i/o mipi tx data lane 3 negative output h6 dognd ground ground for digital circuit table 1-1 signal descriptions (sheet 2 of 3) pin number signal name pin type description 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-3 h7 siod i/o sccb data i/o h8 vsync i/o vsync output h9 dvdd power power for digital circuit j1 nc ? no connect j2 egnd ground ground for mipi circuit j3 pvdd power power for analog circuit j4 mcn i/o mipi tx clock lane negative output j5 mdp3 i/o mipi tx data lane 3 positive output j6 dvdd power power for digital circuit j7 extclk input system input clock j8 sid input sccb address selection 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 j9 nc ? no connect table 1-2 configuration under various conditions (sheet 1 of 2) pin signal name reset a after reset release b software standby c hardware standby d b5 xshutdown input input input input c5 pwdnb input input input input c7 gpio high-z high-z high-z by default (configurable) high-z by default (configurable) e9 frex high-z high-z high-z by default (configurable) high-z by default (configurable) f2 mdp0 high-z high high by default (configurable) high by default (configurable) f3 mdn0 high-z high high by default (configurable) high by default (configurable) f4 mdp1 high-z high high by default (configurable) high by default (configurable) f5 mdn1 high-z high high by default (configurable) high by default (configurable) f7 strobe low low low by default low by default table 1-1 signal descriptions (sheet 3 of 3) pin number signal name pin type description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 f8 tm input input input input f9 fsin high-z high-z high-z by default (configurable) high-z by default (configurable) g2 mdp2 high-z high high by default (configurable) high by default (configurable) g6 sioc high-z input input high-z g8 href high-z high-z high-z by default (configurable) high-z by default (configurable) h2 mdn2 high-z high high by default (configurable) high by default (configurable) h4 mcp high-z high high by default (configurable) high by default (configurable) h5 mdn3 high-z high high by default (configurable) high by default (configurable) h7 siod open drain i/o i/o open drain h8 vsync high-z high-z high-z by default (configurable) high-z by default (configurable) j4 mcn high-z high high by default (configurable) high by default (configurable) j5 mdp3 high-z high high by default (configurable) high by default (configurable) j7 extclk high-z input input high-z j8 sid input input input input a. xshutdown = 0 b. xshutdown from 0 to 1 c. sensor set to sleep from streaming mode d. sensor set to hardware standby fr om streaming mode by pulling pwdnb = 0 table 1-2 configuration under various conditions (sheet 2 of 2) pin signal name reset a after reset release b software standby c hardware standby d 10.23.2013 preliminary specification propr ietary to omnivision technologies 1-5 figure 1-1 pin diagram table 1-3 pad symbol and equivalent circuit (sheet 1 of 2) symbol equivalent circuit extclk siod a1 nc a2 dvdd a3 avdd a4 dovdd a5 atest0 a6 dvdd a7 il_pwm a8 avdd a9 nc b1 agnd b2 dognd b3 dognd b4 avdd b5 xshutdown b6 dognd b7 pvdd b8 dvdd b9 dvdd c1 avdd c2 vh c3 vn c4 dvdd c5 pwdnb c6 nc c7 gpio c8 agnd c9 dognd d1 nc d9 nc e1 dvdd e9 frex f1 dognd f2 mdp0 f3 mdn0 f4 mpd1 f5 mdn1 f6 dovdd f7 strobe f8 tm f9 fsin g1 agnd g2 mdp2 g3 evdd g4 evdd g5 egnd g6 sioc g7 dovdd g8 href g9 dognd h1 avdd h2 mdn2 h3 egnd h4 mcp h5 mdn3 h6 dognd h7 siod h8 vsync h9 dvdd j1 nc j2 egnd j3 pvdd j4 mcn j5 mdp3 j6 dvdd j7 extclk j8 sid j9 nc OV4689 4689_csp5_ds_1_1 pad en dognd from core to core open-drain pd1 pad dognd color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 sioc vsync, strobe, frex, fsin, gpio vn, vh mdp3, mdp2, mdp1, mdp0, mdn3, mdn2, mdn1, mdn0, mcp, mcn, egnd, agnd, dognd avdd, evdd, dvdd, dovdd, pvdd pwdnb xshutdown, sid, tm table 1-3 pad symbol and equivalent circuit (sheet 2 of 2) symbol equivalent circuit pd1 pad dognd din dout en pd2 dognd pad dovdd pad dognd pad dognd pad dognd pad dognd dognd dovdd dovdd dognd pad dognd dognd 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-1 2 system level description 2.1 overview the OV4689 color image sensor is a high performance, 4 megapixel raw image sensor that delivers 2688x1520 at 90 fps using omnibsi-2? pixel technology. users can program image resolution, frame rate, image quality parameters and camera functions are controlled using the indus try standard serial camera control bus (sccb). the OV4689 provides various kinds of hdr modes to increas e dynamic range as well as maintain higher frame rate. all required image processing functions are programmable through the sccb interface. in addition, omnivision image sensors utilize proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. 2.2 architecture the OV4689 sensor core generates streaming pixel data at a constant frame rate. figure 2-1 shows the functional block diagram of the OV4689 image sensor. the timing generator outputs clocks to access the rows of t he imaging array, pre charging and sampling the rows of the array sequentially. in the time between pre charging and sa mpling a row, the charge in the pixels decreases with exposure to incident light. this is the expo sure time in rolling shutter architecture. the exposure time is controlled by adjus ting the time interval between pre charging and sampling. after the data of the pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. following a nalog processing is the adc which outputs up to 10-bit data for each pixel in the array. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-1 OV4689 block diagram OV4689 image sensor core image sensor processor image output interface pll plls control register bank sccb interface timing generator and system control logic extclk sioc sid siod tm xshutdown pwdnb fsin frex strobe vsync gpio href mcp/n mdp/n[3:0] 4689_ds_2_1 column sample/hold row select gain control temperature sensor image array amp otp_dpc 10-bit adc fifo mipi 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-3 figure 2-2 reference schematic note 1 note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note 11 note 12 note 13 note 14 pwdnb should be pulled high to dovdd outside of module if unused. xshutdown(xshutdn) should be connected to dovdd outside of module if unused. for other pins, such as il_pwm, frex, fsin, if unused, can leave floating. avdd is 2.6~3.0v for sensor analog power (clean). dovdd is 1.7~3.0v for sensor digital io power (clean). 1.8v is recommended. dvdd is 1.1~1.3v for sensor digital core power (clean). sensor agnd and dgnd should be separated and connected to a single point outside pcb (do not connect inside the module). dgnd and egnd should be two separated nets, and only connected at a single point. dvdd and evdd should be two separated nets, and only connected at a single point. capacitors should be close to their related sensor pins. evdd/egnd are power/ground for mipi core. mcp and mcn are mipi clock lane positive and negative output. mdpx and mdnx are mipi data lane positive and negative output. traces of mcp, mcn, mdpx and mdnx should have the same or similar length. differential impedance of the clock pair and data pair transmission lines should be controlled at 100 ohm. sid pin should be pulled high for device address 0x20 and pulled low for device address 0x6c. all nc pins can be left floating or connected to gnd if needed. af_vcc and af_agnd is the power supply for auto focus related circuitry. af_vcc can be 2.8~3.3v. u1 OV4689 csp5 agnd b1 agnd g1 avdd h1 avdd c1 dognd f1 dvdd e1 mdp2 agnd egnd dgnd dvdd a2 mdp2 g2 mdn2 mdn2 h2 dognd b2 egnd j2 mdp0 mdp0 f2 mdn0 vh vh c2 mdn0 f3 vn vn c3 evdd g3 avdd a3 dognd b3 pvdd j3 dvdd c4 egnd h3 evdd g4 mcp dovdd a4 mcp h4 mcn mcn j4 mdp1 avdd b4 mdp1 f4 mdn1 mdn1 f5 pwdnb pwdnb c5 egnd g5 mdp3 atest0 a5 mdp3 j5 mdn3 nc a1 mdn3 h5 xshutdn xshutdown b5 dovdd f6 dognd h6 dvdd a6 dvdd j6 sioc sioc g6 strobe dognd b6 strobe f7 dovdd g7 extclk nc a9 extclk j7 nc d1 nc j9 siod gpio gpio c7 siod h7 il _ pwm il_pwm a7 tm f8 href nc d9 href g8 vsync pvdd b7 vsync h8 sid dvdd b8 sid j8 frex frex e9 fsin avdd a8 fsin f9 agnd c8 dognd g9 dognd c9 dvdd b9 dvdd h9 dovdd avdd avdd dvdd dovdd pvdd evdd pvdd dvdd dgnd agnd nc j1 jp1 hrs fx12b-40s-0.4sv (mated connector fx12b-40p-0.4sv) 2 1 agnd 4 3 6 5 siod strobe avdd sid af _ agnd af _ vcc gpio 8 7 sioc 10 9 xshutdn 12 11 14 mdn2 mdp2 13 16 15 18 17 pwdnb href vsync dgnd mdn1 mdp1 20 19 mcp 22 21 mcn 24 23 dgnd 26 25 mdp0 28 27 mdn0 30 29 dgnd 32 31 extclk 34 33 fsin frex il _ pwm mdp3 mdn3 dvdd 36 35 dovdd 38 37 dgnd 40 39 dgnd af _ vcc u2 ad5823 pwdnb pwdn a2 isink a1 siod sda b2 agnd b1 sioc af _ agnd scl c2 vdd c1 l1 8.5x8.5 vcm -+ c8 0.1f-0201 agnd egnd dgnd vn vh dvdd evdd avdd dvdd dovdd evdd pvdd avdd pvdd c1 0.1f-0201 c2 0.1f-0201 c3 0.1f-0201 c4 0.1f-0201 c5 1f-0201 c6 0.1f-0201 c7 0.1f-0201 4689_cob_ds_2_2 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.3 format and frame the OV4689 supports raw rgb output with one/two/four lane mipi interface. table 2-1 non hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688x1520 90 fps 1000 mbps/lane full 1280x720 180 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 1920x1080 120 fps 1000 mbps/lane cropping 672x380 330 fps 1000 mbps/lane 4x4 binning or 4:1 skipping table 2-2 staggered hdr mode frame rate resolution 10-bit output 10-bit output mipi 4 lanes methodology 2688 x 1520 staggered 2 45 fps 1000 mbps/lane full 1280x720 staggered 2 90 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 2688 x 1520 staggered 3 30 fps 1000 mbps/lane full 1280x720 staggered 3 60 fps 1000 mbps/lane 2x2 binning or 2:1 skipping 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-5 2.4 i/o control the OV4689 can configure its i/o pad as an input or output. for the output signal, it follows one of two paths either from the data path or from register control. 2.5 mipi interface the OV4689 supports a mipi interface of up to 4-lanes. the mipi interface can be configured for 1/2/3/4-lane. table 2-3 i/o control registers function register description output drive capability control 0x3011 bit[6:5]: i/o pin drive capability 00: 1x 01: 2x 10: 3x 11: 4x href i/o control 0x3002 bit[6]: href output enable 0: input 1: output href output select 0x3010 bit[6]: enable href as gpio controlled by register href output value 0x300d bit[6]: register control href output gpio i/o control 0x3002 bit[0]: gpio0 output enable 0: input 1: output gpio output select 0x3010 bit[0]: enable gpio as gpio controlled by register gpio output value 0x300d bit[0]: register control gpio output vsync i/o control 0x3002 bit[7]: vsync output enable 0: input 1: output vsync output select 0x3010 bit[7]: enable vsync as gpio controlled by register vsync output value 0x300d bit[7]: register control vsync output color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.6 power management based on the system power configuration (resetb, pw dn control), the power up sequence will be different. omnivision recommends cutting off all power supplies, including the external dv dd, when the sensor is not in use. 2.6.1 power up sequence to avoid any glitch from a strong external noise source, omnivision reco mmends controlling xshutdown or pwdnb by gpio and tie the other pin to dovdd. whether or not xshutdown is cont rolled by gpio, the xshutdown rising cannot occur before avdd, and dovdd. table 2-4 power up sequence case xshutdown pwdnb power up sequence requirement 1gpio dovdd refer to figure 2-3 1. dovdd rising must occur before dvdd rising 2. avdd rising can occur before or after dovdd rising 3. avdd must occur before dvdd 4. xshutdown rising must occur after avdd, dovdd and dvdd are stable 2dovdd gpio refer to figure 2-4 1. avdd rising occurs before dovdd rising 2. dovdd rising occurs before dvdd 3. pwdnb rising occurs after dvdd rising table 2-5 power up sequence timing constraints constraint label min max unit avdd rising ? dovdd rising t0 0 ns dovdd rising ? avdd rising t1 ns xshutdown rising ? first sccb transaction t2 8192 extclk cycles minimum number of extclk cycles prior to the first sccb transaction t3 8192 extclk cycles entering streaming mode ? first frame start sequence (fixed part) t5 10 ms entering streaming mode ? first frame start sequence (variable part) t6 delay is the exposure time value lines avdd or dovdd, whichever is last ? dvdd t7 0 ns dvdd ? pwdnb rising t8 0 ns dvdd ? xshutdown rising t9 0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-7 figure 2-3 power up sequence (case 1) dovdd power off state software standby streaming (active) hardware standby pwdnb (connect to dovdd) avdd (dovdd rising first) extclk (free running) avdd (avdd rising first) extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. dovdd and avdd may rise in any order. t3 t2 t5 (fixed) t6 (variable) t0 t1 dvdd t7 t9 4689_ds_2_3 xshutdown color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-4 power up sequence (case 2) dovdd power off state software standby streaming (active) hardware standby xshutdown (connect to dovdd) avdd extclk (free running) pwdnb extclk (gated) siod sioc mipi lp00 lp01 lp11 lp10 lp00 extclk may either be free running or gated. the requirement is that extclk must be active for time t3 prior to the first sccb transaction. t3 t2 t5 (fixed) t6 (variable) t0 t8 dvdd t7 4689_ds_2_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-9 2.6.2 power down sequence the digital and analog supply voltages can be powered down in any order (e.g. dovdd, then avdd or avdd, then dovdd). similar to the power up sequence, the extclk i nput clock may be either gated or continuous. if the sccb command to exit streaming is received while a frame of mipi da ta is being output, then the sensor must wait to the mipi frame end code before entering software standby mode. if the sccb command to exit streaming mode is received dur ing the inter frame time, then the sensor must enter software standby mode immediately. table 2-6 power down sequence case xshutdown pwdnb power down sequence requirement 1gpio dovdd refer to figure 2-6 1. software standby recommended 2. pull xshutdown low for minimum power consumption 3. cut off dvdd 4. pull avdd and dovdd low in any order 2 dovdd gpio refer to figure 2-7 1. software standby is needed 2. pull pwdnb low for low power consumption 3. cut off dvdd 4. pull dovdd low (xshut down connected to dovdd) 5. pull avdd low color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-7 power down sequence timing constraints constraint label min max unit enter software standby sccb command device in software standby mode t0 when a frame of mipi data is output, wait for the mipi end code before entering the software for standby; otherwise, enter the software standby mode immediately minimum of extclk cycles after the last sccb transaction or mipi frame end t1 512 extclk cycles last sccb transaction or mipi frame end, xshutdown falling t2 512 extclk cycles xshutdown falling ? avdd falling or dovdd falling whichever is first t3 0.0 ns avdd falling ? dovdd falling t4 avdd and dovdd may fall in any order, the falling separation can vary from 0 ns to infinity ns dovdd falling ? avdd falling t5 ns pwdnb falling ? dovdd falling t6 0.0 ns xshutdown falling ? dvdd falling t7 0.0 ns dvdd falling ? avdd falling or dovdd falling whichever is first t8 0.0 ns pwdnb falling ? dvdd falling t9 0.0 ns 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-11 figure 2-5 software standby sequence mcp/mcn mipi mipi mdp/mdn sioc siod lp-11 (high) enter software sccb command received during the readout of the frame then the sensor must wait after the mipi end of frame short packet before entering software standby mode. t1 state software standby streaming (active) lp-11 (high) mcp/mcn mdp/mdn sioc siod lp-11 (high) enter software sccb command is received during the inter frame time sensor enters software standby mode immediately. t1 state software standby streaming (active) lp-11 (high) 4689_ds_2_5 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 2-6 power down sequence (case 1) extclk (free running) avdd (dovdd falling first) avdd (avdd falling first) dovdd extclk (gated) siod sioc t1 if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclkmust be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. dovdd and avdd may fall in any order. t0 t2 t3 t4 t5 power off state software standby streaming (active) hardware standby t7 t8 dvdd pwdnb (connect to dovdd) 4689_ds_2_6 xshutdown 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-13 figure 2-7 power down sequence (case 2) 2.7 reset the whole chip will be reset during power up. 2.7.1 power on reset in this sensor a power on reset is generated after the core power becomes stable. 2.7.2 software reset when register 0x0103[0] is configured as 1, all registers are reset to default value. extclk (free running) avdd (dovdd falling first) dvdd dovdd extclk (gated) siod sioc t1 enter sleep if sccb command received during the readout of the frame then the sensor must wait after the mipi frame end short packet before entering sleep mode. if the sccb command is received during the inter frame time the sensor must enter sleep mode immediately. extclk may either be free running or gated. the requirement is that extclk must be active for time t1 after the last sccb transaction or after the mipi frame end short packet, whichever is the later event. t0 t2 t5 power off state software standby streaming (active) hardware standby t8 t6 4689_ds_2_7 pwdnb xshutdown (connect to dovdd) color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.8 hardware and software standby two suspend modes are available for the OV4689: ? hardware standby ? software standby 2.8.1 hardware standby to initiate hardware standby mode, the xshutdown or pwdnb pin must be tied to low. when this occurs, the OV4689 internal device clock is halted even when t he external clock source is still clocking and all internal counters are reset. with "pwdnb" control, the sensor regi ster setting can be maintained and the sensor is in low power consumption mode. with "xshutdown" mode the sensor is in power cut mode, no register settings are kept and the sensor is in minimum power consumption. 2.8.2 software standby when the software standby (0x0100[0]) control is enabled throug h the sccb interface, all f unction blocks are in standby mode except the sccb slave. table 2-8 hardware and standby description mode description hardware standby with pwdnb 1. enabled by pulling pwdnb low 2. input clock is gated by pwdnb, no sccb communication 3. register values are maintained 4. power down all blocks and regulator 5. low power consumption 6. gpio can be configured as high/low/tri-state hardware standby with xshutdown 1. enabled by pulling xshutdown low 2. power down all blocks 3. register values are reset to default values 4. no sccb communication 5. minimum power consumption software standby 1. default mode after power on reset 2. power down all blocks except sccb and regulator 3. register values are maintained 4. sccb communication is available 5. low power consumption 6. gpio can be configured as high/low/tri-state 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-15 2.9 system clock control 2.9.1 pll1 the pll1 generates a default 126 mhz pixel clock and 1008mhz mi pi serial clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmabl e clock is provided to gener ate different frequencies. 2.9.2 pll2 the pll2 generates a default 120 mhz syst em clock from a 6~64 mhz input clock. the vco range is from 600 mhz to 1200 mhz. a programmable clock divider is provided to generate different frequencies. figure 2-8 pll structure table 2-9 pll speed limitation parameter value pll1_multiplier input 4~27 mhz pll1_multiplier output 600~1200 mhz pll2_multiplier input 4~27 mhz pll2_multiplier output 600~1200 mhz sclk 10~126 mhz pclk 10~150 mhz dac 360~378 mhz pll1_predivp 1/2 pll2_predivp 1/2 pll1_prediv 1/1.5/2/2.5/3/4/6/8 pll1_multiplier 1 ~ 1023 pll2_multiplier 1 ~ 1023 pll1_divsp 3/4/5/6 pll1_divs 1/2 pll1_div_mipi 4/5/6/8 pll1_divm 1 ~ 16 pll2_divdac 1 ~ 16 dac_clk (mbps) extclk 6 ~ 64 mhz pll1 pll2 sclk (option) 3103[2] = 0 pclk mipi_phy_clk 600 ~ 1200 mhz 4 ~ 27 mhz 4 ~ 27 mhz pll2_prediv 1/2.5/2/2.5/3/4/6/8 pll2_divsp 1 ~ 16 pll2_divs 1/1.5/2/2.5/3/3.5/4/5 extclk 6 ~ 64 mhz sclk (default) max: 126 mhz 600 ~ 1200 mhz 4689_ds_2_8 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 2-10 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[2:0]: pll1_prediv 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x0301 pll_ctrl_1 0x00 rw bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[3:0]: pll1_divm 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0304 pll_ctrl_4 0x03 rw bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[1:0]: pll1_divsp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[0]: pll1_div_s 0: /1 1: /2 0x0308 pll_ctrl_8 0x00 rw bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[2:0]: pll1_cp 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-17 0x030a pll_ctrl_a 0x00 rw bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[2:0]: pll2_prediv 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 4 110: 6 111: 8 0x030c pll_ctrl_c 0x00 rw bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[2:0]: pll2_divs 000: 1 001: 1.5 010: 2 011: 2.5 100: 3 101: 3.5 110: 4 111: 5 0x030f pll_ctrl_f 0x01 rw bit[3:0]: pll2_divsp 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x0310 pll_ctrl_10 0x01 rw bit[2:0]: pll2_r_cp 0x0311 pll_ctrl_11 0x00 rw bit[0]: pll2_predivp 0: /1 1: /2 table 2-10 pll registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x0312 pll_ctrl_12 0x01 rw bit[4]: pll2_bypass bit[3:0]: pll2_divdac 0000: /1 0001: /2 0010: /3 0011: /4 0100: /5 0101: /6 0110: /7 0111: /8 1000: /9 1001: /10 1010: /11 1011: /12 1100: /13 1101: /14 1110: /15 1111: /16 0x031b pll_ctrl_1b 0x00 rw bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[0]: pll2_rst 0x031f pll_ctrl_1f 0x00 rw bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 2-11 sample pll configuration (sheet 1 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz pll1_predivp 0x030a[0] 0x0 0x0 0x0 pll1_prediv 0x0300[2:0] 0x7 0x0 0x0 pll1_multiplier {0x0301[1:0], 0x0302[7:0]} 0x7e 0x2a 0xa8 pll1_div_mipi 0x0304[1:0] 0x3 0x3 0x3 pll1_divm 0x0303[3:0] 0x0 0x0 0x0 pll1_divsp 0x0305[1:0] 0x1 0x1 0x1 pll1_divs 0x0306[0] 0x1 0x1 0x1 pll2_predivp 0x0311[0] 0x0 0x0 0x0 pll2_prediv 0x030b[2:0] 0x5 0x0 0x0 table 2-10 pll registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-19 2.10 serial camera control bus (sccb) interface the serial camera control bus (sccb) interface co ntrols the image sensor operation. refer to the omnivision technologies serial camera co ntrol bus (sccb) specification for detailed usage of the serial control port. in the OV4689, the sccb id is controlled by the sid pin. if sid is low, the sensor?s sccb address comes from register 0x3004 which has a default value of 0x6c. if sid is high, the sensor?s sccb a ddress comes from register 0x3012 which has a default value of 0x20. 2.10.1 data transfer protocol the data transfer of the OV4689 follows the sccb protocol. 2.10.2 message format the OV4689 supports the message format shown in figure 2-9 . the repeated start (sr) condition is not shown in figure 2-10 , but is shown in figure 2-11 and figure 2-12 . figure 2-9 message type pll2_multiplier {0x030c[1:0], 0x030d[7:0]} 0x2d 0x1e 0x78 pll2_divsp 0x030f[3:0] 0x1 0x1 0x1 pll2_divs 0x030e[2:0] 0x4 0x4 0x4 sclk ? 120 mhz 120 mhz 120 mhz mipi_sclk ? 1008 mhz 1008 mhz 1008 mhz mipi_pclk ? 126 mhz 126 mhz 126 mhz table 2-11 sample pll configuration (sheet 2 of 2) control name address input clock (extclk) 64 mhz 24 mhz 6 mhz slave address s r/w a a a sub address [15:8] sub address [7:0] a/a p data index[15:8] index[7:0] from slave to master from master to slave direction depends on operation s start condition p stop condition sr repeated start condition a acknowledge negative acknowledge a message type: 16-bit sub-address, 8-bit data, and 7-bit slave address 4689_ds_2_9 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.10.3 read / write operation the OV4689 supports four different read operations and two different write operations: ? a single read from random locations ? a sequential read from random locations ? a single read from current location ? a sequential read from current location ? single write to random locations ? sequential write starting from random location the sub-address in the sensor automatically increas es by one after each read/write operation. in a single read from random locations, the master does a dummy write operation to des ired sub-address, issues a repeated start condition and then addresses the camera again with a read operation. after acknowledging its slave address, the camera starts to output data onto the siod line as shown in figure 2-10 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-10 sccb single read fr om random location if the host addresses the camera with read operation directly without the dummy write operation, the camera responds by setting the data from last used sub- address to the siod line as shown in figure 2-11 . the master terminates the read operation by setting a negativ e acknowledge and stop condition. figure 2-11 sccb single read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address a p data index m previous index value, k index m + 1 index value m 4689_ds_2_10 slave address s 1 a a s 1 slave address data a p a p data index k + 1 index k + 2 previous index value, k 4689_ds_2_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-21 the sequential read from a random location is illustrated in figure 2-12 . the master does a dummy write to the desired sub-address, issues a repeated start co ndition after acknowledge from slave a nd addresses the slave again with read operation. if a master issues an acknowledge after receiving data , it acts as a signal to the slave that the read operation shall continue from the next sub-address. when master has read the last data byte, it issues a negative acknowledge and stop condition. figure 2-12 sccb sequential read from random location the sequential read from current location is similar to a sequential read from a random loca tion. the only exception is that there is no dummy write operation, as shown in figure 2-13 . the master terminates the read operation by setting a negative acknowledge and stop condition. figure 2-13 sccb sequential read from current location slave address s 0 a a a a sub address [15:8] sub address [7:0] sr 1 slave address data a a p data index m previous index value, k index m + l - 1 index m + l index value m l bytes of data 4689_ds_2_12 slave address s 1 a a a data data a p data index k + 1 previous index value, k index k + l - 1 index k + l l bytes of data 4689_ds_2_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 the write operation to a random location is illustrated in figure 2-14 . the master issues a write operation to the slave, sets the sub-address and data correspondingly after the slave has acknowledged. the write operation is terminated with a stop condition from the master. figure 2-14 sccb single write to random location the sequential write is illustrated in figure 2-15 . the slave automatically increments the sub-address after each data byte. the sequential write operation is termi nated with stop condition from the master. figure 2-15 sccb sequential write to random location slave address s 0 a a a sub address [15:8] sub address [7:0] data p index m previous index value, k index m + 1 a/a index value m 4689_ds_2_14 slave address s 0 a a a a sub address [15:8] sub address [7:0] data index m previous index value, k index m + l - 1 index m + l data p a/a index value m l bytes of data 4689_ds_2_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-23 2.10.4 sccb timing figure 2-16 sccb interface timing table 2-12 sccb interface timing specifications ab a. sccb timing is based on 400khz mode b. timing measurement shown at the beginning of t he rising edge and/or of the falling edge signifies 30%, timing measurement shown in the middle of the rising/fa lling edge signifies 50%, timing measurement shown at the beginning of the rising edge and/or of the falling edge signifies 70% symbol parameter min typ max unit f sioc clock frequency 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t aa sioc low to data out valid 0.1 0.9 s t buf bus free time before new start 1.3 s t hd:sta start condition hold time 0.6 s t su:sta start condition setup time 0.6 s t hd:dat data in hold time 0 s t su:dat data in setup time 0.1 s t su:sto stop condition setup time 0.6 s t r , t f sccb rise/fall times 0.3 s t dh data out hold time 0.05 s siod (out) siod (in) sioc t aa t dh t hd:dat t su:sto t f t su:sta t r t high t low t hd:sta t buf t su:dat 4689_ds_2_16 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.11 group write group write is supported in order to update a group of regist ers in the same frame. these registers are guaranteed to be written prior to the internal latch at the frame boundary. the OV4689 supports up to four groups. these groups share 102 4x8 bits or 1024 bytes and the size of each group is programmable by adjusting the start address. table 2-13 context switching control (sheet 1 of 2) address register name default value r/w description 0x3208 group access 0x00 rw group access bit[7:4]: group control 0000: group hold start 0001: group hold end 1010: group delay launch 1110: group quick launch others: debug mode bit[3:0]: group id 0000: group bank 0, default start from address 0x00 0001: group bank 1, default start from address 0x40 0010: group bank 2, default start from address 0x80 0011: group bank 3, default start from address 0xb0 others: debug mode 0x3209 grp0_period 0x00 rw bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a grp1_period 0x00 rw frames for staying in second group (can be group 1-3) 0 means always stay in second group 0x320b grp_swctrl 0x01 rw bit[7]: auto switch bit[3]: group_switch_repeat_enable enable the first group (group 0) and second group repeatable switch bit[2]: context_enable enable to switch from second group back to first group (group 0) automatically bit[1:0]: second group selection 00: group 0 01: group 1 10: group 2 11: group 3 0x320d grp_act ? r indicates which group is active 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-25 2.12 hold after the groups are configured, users can perform a hold oper ation to store register settings into the sram of each group. the hold of each group starts and ends with the control register 0x3208. the lower 4 bi ts of register 0x3208 control which group to access, and the upper 4 bits control the start (0x0: hold start) and end (0x1: hold end) of the hold operation. the example setting below show s the sequence to hold group 0: 6c 3208 00 group 0 hold start 6c 3800 11 first register into group 0 6c 3911 22 second register into group 0 6c 3208 10 group 0 hold end 2.13 launch after the contents of each group are defined in the hold operati on, all registers belonging to each group are stored in sram, and ready to be written into target registers (i.e., the launch of that group). there are five launch m odes as described section section 2.13.1 to section 2.13.5 . 2.13.1 launch mode 1 - quick manual launch manual launch is enabled by setti ng the register 0x320b to 0. quick manual launch is achieved by writing to control register 0x3208. the val ue written into this register is 0xex, the upper 4 bits (0xe) are the quick launch command and the lowe r 4 bits (0xx) are the group number. for example, if users want to launch group 0, they just write the value 0xe0 to 0x3208, then the contents of group 0 will be written to the target registers immediately after the sensor gets this co mmand through the sccb. below is an example setting. 6c 320b 00 manual launch on 6c 3208 e0 quick launch group 0 0x320e frame_cnt_grp0 ? r frame count group 0 0x320f frame_cnt_grp1 ? r frame count group 1 table 2-13 context switching control (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 2.13.2 launch mode 2 - delay manual launch delay manual launch is achieved by writing to the register 0x3208. the value written into this register is 0xax, where the upper 4 bits (0xa) are the delay launch command and the lower 4 bits (0xx) are the group number. for example, if users want to launch group 1, they just write the value 0xa1 to 0x 3208, then the contents of group 1 will be written to the target registers. the difference with mode 1 is t hat the writing will wait for some internal ly defined time spot in vertical blanking, thus delayed. below is an example setting. 6c 320b 00 manual launch on 6c 3208 a1 delay launch group 1 2.13.3 launch mode 3 - quick auto launch quick auto launch works like the mode 1, the difference is it will return to a specifi ed group automatically. this is controlled by the register 0x3209, where bit[6:5] controls whic h group to return and bit[4:0] controls how many frames to stay before returning. the auto launch enable bit is the 0x320b[7]. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 e0 quick launch group 0 in this example, sensor wi ll quick launch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.4 launch mode 4: delay auto launch delay auto launch works like mode 2 in the delay launch part and like the mode 3 in the return part. the operation can be better understood with an example setting: 6c 3209 44 bit[6:5]: 2, return to group 2, bit[4:0]: 4: stay 4 frames 6c 320b 80 auto launch on 6c 3208 a0 delay launch group 0 in this example, sensor will delay l aunch group 0, stay at group 0 for 4 frames, then return to group 2 after that. 2.13.5 launch mode 5: repeat launch repeat launch is controlled by regist ers 0x3209, 0x320a, and 0x320b. in this mode, the launch is repeated automatically between the first group (must be group 0) and the second grou p (can be either one of groups 1- 3, which is specified by register 0x320b[1:0]). the register 0x3209 defines how many frames remain at group 0, and register 0x320a defines how many frames remain at the second group. the operation can be better understood with an example setting: 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7]: 3, stay 3 frames in the second group 6c 320b 0e bit[3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch 10.23.2013 preliminary specification propr ietary to omnivision technologies 2-27 in this example, sensor will delay launch group 0, stay at group 0 for 2 frames, then switch to group 2 for 3 frames, then back to group 0 for 2 frames, group 2 for 3 frames and so on. below is another example to apply launch mode 2 (delay manual launch) first, sensor stays at group 2 for an indefinite number of frames, then apply launch mode 5 (repeat launch). the sensor will switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. 6c 320b 00 manual launch on 6c 3208 a2 delay launch group 2 stay at group 2 for indefinite frames 6c 3209 02 bit[7:0]: 2, stay 2 frames in group 0 6c 320a 03 bit[7:0]: 3, stay 3 frames in the second group 6c 320b 0e bit3:2]: 3, repeat launch on, bit[1:0]: 2, second group select: group 2 6c 3208 a0 always use a0 for repeat launch switch to group 0 for 2 frames, then group 2 for 3 frames, and so on. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-1 3 block level description 3.1 pixel array structure the OV4689 sensor has an image array of 2720 columns by 1584 rows (4,308,480 pixels). figure 3-1 shows a cross-section of the image sensor array. the color filters are arranged in a bayer pattern. the primary color bg/gr array is arranged in line-alternating fashion. of the 4,308,480 pixels, 4,177,920 (2720x1536) are active pixels and can be output. the other pixels are used for black level calibration and interpolation. the center 2688x1520 pixels is suggested to be output from the whole active pixel array. the backend processor can use th e boundary pixels for a dditional processing. the sensor array design is based on a fiel d integration readout system with line-by -line transfer and an electronic shutter with a synchronous pixel readout scheme. figure 3-1 sensor array region color filter layout 0 1 2 3 2706 2707 ... 2719 0 1 2 3 ... 23 24 25 26 27 31 32 33 34 35 ... ... ... 1551 1552 1553 1554 1555 1559 ... 1560 1561 1562 1563 1583 rows columns ... 15 16 17 18 19 ... 2703 2704 2705 24 black lines 24 black lines 8 dummy lines 1520 active lines 8 dummy lines 2688 active pixels 16 dummy pixels 16 dummy pixels b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r 4689_ds_3_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 3.2 subsampling the OV4689 supports a binning mode to provide a lower resolu tion output while maintaining the field of view. with binning mode on, the voltage levels of adjacent pixels (of the same color) are averaged before being sent to the adc. the OV4689 supports 2x2 binning, and 4x4 binning which is illustrated in figure 3-2 and figure 3-2 , where the voltage levels of two horizontal (2x1) adjac ent same-color pixels are averaged. figure 3-2 example of 2x2 binning figure 3-3 example of 4x4 binning b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 2x2 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 2x2 binned into 1 four green pixels 2x2 binned into 1 four red pixels 2x2 binned into 1 4689_ds_3_2 b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r four blue pixels 4x4 binned into 1 b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g b g g r b g g r b g g r b g g r b g four green pixels 4x4 binned into 1 four green pixels 4x4 binned into 1 four red pixels 4x4 binned into 1 4689_ds_3_3 10.23.2013 preliminary specification propr ietary to omnivision technologies 3-3 3.3 analog amplifier when the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. 3.4 10-bit a/d converters the balanced signal is then digiti zed by the on-chip 10-bit adc. table 3-1 binning-related registers address register name default value r/w description 0x3820 timing_format1 0x10 rw bit[0]: vertical binning 0x3821 timing_format2 0x08 rw bit[0]: horizontal binning color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-1 4 image sensor core digital functions 4.1 mirror and flip the OV4689 provides mirror and flip readout modes, whic h respectively reverse the sensor data readout order horizontally and vertically (see figure 4-1 ). figure 4-1 mirror and flip samples table 4-1 mirror and flip registers address register name default value r/w description 0x3820 format1 0x00 rw timing control register bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip 0x3821 format2 0x00 rw timing control register bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror f original image f flipped image f mirrored image f mirrored and flipped image 4689_ds_4_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.2 image cropping and windowing an image cropping area is defined by four parameters , horizontal_crop_start (hs), horizontal_crop_end (he), vertical_crop_start (vs), and vertical_c rop_end (ve). by properly setting the para meters, any portion within the sensor array size can output as a visible area. windowing is achieved by masking off the pixels outside of this cropping window using h_win_off and v_win_off parameters (see figure 4-2 ); thus, the original timing is not affected. figure 4-2 image cropping and windowing table 4-2 image cropping and windowing co ntrol functions (sheet 1 of 2) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x20 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x0c rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x12 rw bit[4:0]: horizontal crop end address[12:8] sensor array vertical output size v_crop_start (vs) v_crop_end (ve) v_win_off v_output_size h_output_size sensor array horizontal output size h_win_off h_crop_start (hs) h_crop_end (he) 4689_ds_4_2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-3 0x3805 h_crop_end 0x3f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x0d rw bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0x8c rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x12 rw bit[4:0]: horizontal output size[12:8] 0x3809 h_output_size 0x00 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x0d rw bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0x80 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x05 rw bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0xf8 rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x0d rw bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0xa4 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x01 rw bit[7:0]: ho rizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x00 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[4:0]: horizontal sub-sample even increase number 0x382a v_inc_odd 0x01 rw bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[4:0]: vertic al sub-sample even increase number table 4-2 image cropping and windowing control functions (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.3 test pattern for testing purposes, the OV4689 offers three types of test patterns: color bar, square and random data. the OV4689 also offers two digital effects: transparent effect and rolling bar effect. the output type of digital test pattern is controll ed by the test_pattern_type register (0x5040[3:2]). the digital test pattern function is cont rolled by register 0x5040[7]. 4.3.1 color bar there are four types of color bars (see figure 4-3 ) which are switched by bar-style in register 0x5040[3:2]. figure 4-3 color bar types 4.3.2 square there are two types of squares: color square and black-white square (see figure 4-4 ). the squ_bw register (0x5040[4]) determines which type of square will be output. figure 4-4 color, black and white square bars color bar type 1 0x5040[3:2]=2'b00 color bar type 2 0x5040[3:2]=2'b01 color bar type 4 0x5040[3:2]=2'b11 color bar type 3 0x5040[3:2]=2'10 4689_ds_4_3 color square black-white square 4689_ds_4_4 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-5 4.3.3 random data there are two types of random data test patte rns: frame-changing and frame-fixed random data. 4.3.4 transparent effect the transparent effect is enabled by transparent_en register (0 x5040[5]). if this register is set, the transparent test pattern will be displayed. the image in figure 4-5 is an example which shows a transparent color bar image. figure 4-5 transparent effect 4.3.5 rolling bar effect the rolling bar is set by rolling_bar_en register (0x5040[6]). if it is set, a inverted-color rolling bar will roll from up to down. the image in figure 4-6 is an example which shows a rolling bar on color bar image. figure 4-6 rolling bar effect 4689_ds_4_5 4689_ds_4_6 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-3 test pattern registers address register name default value r/w description 0x5040 pre ctrl00 0x00 rw bit[7]: test pattern enable 0: disable test function 1: enable test function bit[6]: rolling bar enable 0: disable 1: enable bit[5]: transparent enable 0: disable 1: enable bit[4]: square mode 0: color square 1: black-white square bit[3:2]: color bar style 00: standard color bar 01: top-bottom darker color bar 10: right-left darker color bar 11: bottom-top darker color bar bit[1:0]: test pattern mode 00: color bar 01: random data 10: square 11: black image 0x5041 pre ctrl01 0x41 rw bit[6]: window cut enable 0: do not cut the redundant pixels 1: cut the redundant pixels bit[4]: same seed enable when set, the seed used to generate the random data are same which is set in seed register bit[3:0]: seed seed used in generating random data 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-7 4.4 gain and exposure control the OV4689 does not support auto exposure control (aec) or auto gain control (agc). both exposure time and gain are set manually. the related registers are listed in table 4-4 . note for optimal performance, maximum exposure should be 200ms. for more details, contact your local omnivision fae. table 4-4 gain/exposure control registers a (sheet 1 of 2) address register name default value r/w description 0x3500 expo 0x00 rw bit[3:0]: expo[19:16] 0x3501 expo 0x02 rw bit[7:0]: expo[15:8] 0x3502 expo 0x00 rw bit[7:0]: expo[7:0] low 4 bits are fraction bits 0x3503 aec manual 0x00 rw aec manual mode control bit[6]: digital fraction gain delay option 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[2]: gain man as sensor gain 0: gain input as real gain format 1: gain input as sensor gain format bit[1]: exposure delay option 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option 0: delay 1 frame 1: no delay 1 frame 0 x3507 aec long gain 0x00 rw long gain bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[3:0]: middle exposure[19:16] 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits 0x350d aec middle gain 0x00 rw middle gain bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits 0x3513 aec short gain 0x00 rw short gain bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits a. for the gain formula, please contact your local omnivision fae table 4-4 gain/exposure control registers a (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-9 4.5 high dynamic range (hdr) mode hdr mode increases image dynamic range by capturing multip le exposures of a similar scene and then combining them into one single image. the OV4689 supports three kinds of hdr mode: ? sequential hdr ? staggered hdr 4.5.1 sequential hdr the OV4689 supports up to five different exposure/gain sets for sequential hdr. in 3-set sequential hdr mode, long/medium/short exposure frames are interlaced as shown in figure 4-7 . a backend chip will take two consecutive frames and combine them into one hdr frame. figure 4-7 sequential hdr mode table 4-5 timing control address register name default value r/w description 0x3829 format 0x00 rw bit[3]: hdr_lite_enable table 4-6 timing control address register name default value r/w description 0x3846 timing_reg_36 0x08 rw bit[2:0]: sequential hdr number frame1 long frame2 medium frame3 short frame4 long frame5 medium frame6 short sof 4689_ds_4_7 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.5.2 staggered hdr in staggered hdr mode, long/medium/short exposure frames ar e overlapping with each other. this reduces the timing delay between different exposure frames, which will combine into one hdr frame. it also reduces the frame/line buffer needed for the backend chip. figure 4-8 and figure 4-9 illustrate the frame timing for 3-set staggered hdr. the OV4689 supports 2-set/3-set staggered hdr mode. the OV4689 uses mipi virtual channel to differentiate diff erent exposure frames. long/medi um/short frame uses mipi virtual channel vc0/vc1/vc2, respec tively, so that different exposure frames will not be mixed up at the mipi receiver side. figure 4-8 staggered hdr with virtual channel the OV4689 also supports different exposure transfers without mipi virtual channel, which is controlled by register 0x3837. figure 4-9 staggered hdr without virtual channel table 4-7 timing control address register name default value r/w description 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[0]: staggered hdr enable frame1_long fs fs fe fe fs fs fe fe fs fs fe fe frame1_medium frame1_short frame2_long frame2_medium frame2_short max_exposure_medium max_exposure_short max_exposure_long 4689_ds_4_8 frame0_long fe fe frame0_medium fe frame0_short frame2_long frame2_medium dummy dummy dummy dummy frame2_short max_exposure_short 4689_ds_4_9 max_exposure_medium fs fe frame1_long frame1_medium dummy dummy dummy dummy frame1_short fs fe dummy dummy frame0_short fe 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-11 4.5.3 average luminance (yavg) exposure time control is based on a frame brightness average value. the OV4689 supports the average image luminance calculation. by properl y setting x_start, y_start, and window_width and window_height as shown in transparent effect, a 4x4 grid average window is defined. it will automatically divide t he window into 4x4 zones. the average value is the weighted average of the 16 sections. table 4-8 lists the corresponding registers. figure 4-10 average-based window definition table 4-8 avg registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg ctrl00 0x00 rw bit[4:0]: x_start_avg[12:8] 0x5681 avg ctrl01 0x00 rw bit[7:0]: x_start_avg[7:0] 0x5682 avg ctrl02 0x00 rw bit[3:0]: y_start_avg[11:8] 0x5683 avg ctrl03 0x00 rw bit[7:0]: y_start_avg[7:0] 0x5684 avg ctrl04 0x11 rw bit[4:0]: window_width_avg[12:8] 0x5685 avg ctrl05 0x00 rw bit[7:0]: window_width_avg[7:0] 0x5686 avg ctrl06 0x09 rw bit[3:0]: window_height_avg[11:8] 0x5687 avg ctrl07 0xa0 rw bit[7:0]: window_height_avg[7:0] sensor array size x 4689_ds_4_10 sensor array size valid pixel (windowing) size sensor array size y (x_start, y_start) (0, 0) window_height window_width color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5688 avg ctrl08 0x11 rw bit[7:4]: weight01 bit[3:0]: weight00 0x5689 avg ctrl09 0x11 rw bit[7:4]: weight03 bit[3:0]: weight02 0x568a avg ctrl0a 0x11 rw bit[7:4]: weight11 bit[3:0]: weight10 0x568b avg ctrl0b 0x11 rw bit[7:4]: weight13 bit[3:0]: weight12 0x568c avg ctrl0c 0x11 rw bit[7:4]: weight21 bit[3:0]: weight20 0x568d avg ctrl0d 0x11 rw bit[7:4]: weight23 bit[3:0]: weight22 0x568e avg ctrl0e 0x11 rw bit[7:4]: weight31 bit[3:0]: weight30 0x568f avg ctrl0f 0x11 rw bit[7:4]: weight33 bit[3:0]: weight32 0x5690 avg ctrl10 0x02 rw bit[1]: sum option 0: sum=(4b+9g2+10r)/8 1: sum=b+g2+r bit[0]: sub-window function enable 0: use whole output window for average 1: use registers 0x5680~0x5687 to define window for average 0x5693 avg roreg2 ? r bit[7:0]: avg high 8 bits of whole image avg output table 4-8 avg registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-13 4.5.4 black level calibration (blc) the pixel array contains several optical ly shielded (black) lines and optically sh ielded (black) pixels on the right side. these lines and columns are used as reference for black le vel calibration. the main functions of the blc are: ? adjusting all normal pixel values bas ed on the values of the black levels ? applying multiplication to all pi xel values based on digital gain black level adjustments can be made wi th registers 0x4000, 0x4004, and 0x4005. table 4-9 blc registers address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: offset out of range triggers blc enable bit[6]: format change triggers blc enable bit[5]: gain change triggers blc enable bit[4]: exposure change triggers blc enable bit[3]: manually trigger blc signal its rising edge will triggers blc bit[2]: blc freeze function enable when set, blc will be frozen and the offsets will keep the pre-frame values bit[1]: blc always triggered enable when set, the blc will be triggered every frame unless the 0x4000[2] is enabled. 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] high bits of blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] low bits of blc target color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.6 one time programmable (otp) memory the OV4689 supports a maximum of 512 bytes of one-time pr ogrammable (otp) memory to store chip identification and manufacturing information, which can be used to update t he sensor's default setting and can be controlled through the sccb (see table 4-10 ). registers 0x7000~0x710f and 0x71cb~0x71ff are reserved for use by omnivision only. registers 0x7110~0x71ca are available for use by customers. 4.6.1 otp other functions otp loading data can be triggered when power up or writing 0x01 to register 0x3d81. power up loading data is controlled by register 0x3d85[2], by default it is off. auto mode and manual mode can be chosen by setting register 0x3d84[6] to 0 and 1, respectively, and by default, it is in auto mode. in au to mode, all data in the otp will be loaded to the otp buffer; while in manual mode, part of the data which is defined by the start address ({0x3d88,0x3d89}) and the end address ({0x3d8a,0x3d8b}) of the otp will be loaded to the otp buffer. the otp memory access conditions are based on typical co nditions, sensor wakeup, 2.6~3.0v avdd, 1.2v dvdd, and 120 mhz system clock. otp access requires special timing. in order for otp ac cess to work with default settings, sclk should be between 114~126mhz. to use otp memory under different operating condi tions, please contact your local omnivision fae. table 4-10 otp control registers (sheet 1 of 2) address register name default value r/w description 0x7000~ 0x71ff otp_sram 0x00 rw bit[7:0]: otp buffer 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[0]: otp_program_enable 0x3d81 otp_load_ctrl 0x00 rw bit[7]: otp_rd_busy bit[5]: otp_bist_error bit[4]: otp_bist_done bit[0]: otp_load_enable 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 1: disable bit[6]: mode select 0: auto mode 1: manual mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-15 4.7 temperature sensor theOV4689 supports an on-chip temperature sensor that co vers -64~192c with an average range of 5c. it can be controlled through the sccb interface (see table 4-11 ). before reading the temperature, the temperature sensor should be triggered by a 0 to 1 transition of register 0x4d12[0]. there is a 64c offset in the readout value. the junction temperature can be calculated by converting the readout value from hex to decimal and minus 64. 0x3d85 otp_reg85 0x13 rw bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode 0x3d8a otp_end_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_address 0x00 rw otp start low address for load setting table 4-11 temperature sensor functions address register name r/w description 0x4d12 tpm trigger rw bit[0]: temperature sensor trigger 0x4d13 tpm read rw bit[0]: temperature readout table 4-10 otp control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8 strobe flash and frame exposure 4.8.1 strobe flash control the strobe signal is programmable using register 0x3b00[ 1:0]. it supports both led and xenon modes. the polarity of the pulse can be changed. the strobe signal is enabled (t urned high/low depending on the pulse 's polarity) by requesting the signal via the sccb interface using register bit 0x3b 00[7]. flash modules are trigger ed by the rising edge by default or by the falling edge if the signal polarity is changed. it su pports the following flashing m odes: xenon flash control, led mode 1, led mode 2 and led mode 3. 4.8.1.1 xenon flash control after a strobe request is submitted, the strobe pulse wi ll be activated at the beginning of the third frame (see figure 4-11 ). the third frame will be correctly exposed. the pulse width can be changed in xenon mode between 1h and 4h using register 0x3b00[5:4], where h is one row period. figure 4-11 xenon flash mode vertical blanking exposure time data out strobe request strobe pulse strobe pulse zoomed request here 1h correctly exposed frame 4689_ds_4_11 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-17 4.8.1.2 led 1/led 2 in led 1/led 2 mode, the strobe signal stays active un til the strobe end request is sent (see led 1 mode). figure 4-12 led 1/ led 2 single frame mode the strobe width is controlled by (0x3b 02, 0x3b03), unit is now period. the strobe pulse will be activated at the beginning of the third frame. figure 4-13 led1/led2 multi-frame mode vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame number of inserted dummy lines is programmable request here start end 4689_ds_4_12 vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame request here start number of inserted dummy lines is programmable 4689_ds_4_13 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 4.8.1.3 led 3 mode in led 3 mode, the strobe signal will be activated at t he beginning of the first frame and the pulse start point can be selected from sof or eof controlled by 0x3b04[3]. the st robe signal stays active until the strobe end request is sent (see figure 4-14 ). figure 4-14 led 3 mode 4.8.1.4 led 4 mode in led 4 mode, the strobe signal width is controlled by register 0x3b05. strobe width = 128 (2^0x3b05[1:0]) (0x3b05[7:2] + 1) sclk_period. the strobe width cannot be longer than v-blanking period. the pulse start point can be selected from sof or eof which is controlled by 0x3b04[3], and strobe timing delay can be controlled by 0x3b04[1:0]. the repeat trigger is su pported by setting 0x3b04[4] to be 1. figure 4-15 led 4 mode vertical blanking exposure time data out strobe request strobe signal correctly exposed frame request here request here start end 4689_ds_4_14 vertical blanking exposure time data out strobe request strobe pulse request here correctly exposed frame 4689_ds_4_15 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-19 4.8.2 frame exposure (frex) mode in frex mode, all pixels in the frame start integration at the same time, rather than integrating row by row. after a user-defined exposure time, the mechanica l shutter should be closed, preventing fu rther integration, and then the image begins to read out. after the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next frex request. the OV4689 supports two modes of frex (see figure 4-16 and figure 4-17 ): figure 4-16 frex mode 1 figure 4-17 frex mode 2 in mode 1, the frex pin is configured as an input while it is configured as an output in mode 2. in both mode 1 and mode 2, the strobe output is irrelevant with the rolling strobe f unction. when in rolling shutter mode, the strobe function and this frex/shutter control function do not work at the same time. the timing diagram for mode 1 is shown in figure 4-18 . sccb data/sync frex shutter strobe sensor system shutter 4689_ds_4_16 sccb data/sync frex strobe sensor system shutter 4689_ds_4_17 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 figure 4-18 frex mode 1 timing diagram in mode 1, the host asserts frex at any time in preview mode (mechanical shutter is open at this time). the sensor will trigger strobe to indicate the start of exposure time. exposure time is calcul ated from the strobe rising edge to when the mechanical shutter closes. the host will control when to close the mechanica l shutter (shutter delay is handled by the host). the host can re-open the shutter after re ceiving the entire image data or the next vsync signal. the timing diagrams for mode 2 are shown in figure 4-19 and figure 4-20 . figure 4-19 frex mode 2 (shutter delay = 0) timing diagram t exp t pchg frex mode 1: pad trigger vsync frex in strobe out shutter 4689_ds_4_18 t exp t pchg t datout_dly shutter close vsync strobe out shutter frex out sccb 4689_ds_4_19 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-21 figure 4-20 frex mode 2 (shutter delay > 0) timing diagram before using mode 2, the host needs to program exposure time (registers 0x37c5, 0x37c 6, 0x37c7), shutter delay (registers 0x37cc, 0x37cd), strobe width (registers 0x37c9, 0x37ca, 0x37cb), and data output delay. the host triggers this mode by sccb at any time in prev iew mode (mechanical shutter is open at this time). the sensor can either start frame exposure right away (since the current data packet is broken, the receiver may get a packet error) or wait for the current frame to finish (controlled by register 0x37df[0]). if there is no strobe delay, the sensor will trigger strobe to indicate the start of exposure time. exposure time is calculated from strobe rising edge to when the mechanical shutter closes. otherwise, the strobe si gnal will be sent out even before the s ensor begins to pre-charge. the host can control the sensor to start sending image data after a ce rtain delay (registers 0x37d0, 0x37d1) after frex goes low. the host can re-open the shutter after receiving the entire image data or the next vsync signal. see table 4-12 for frex strobe control functions. t exp t1 t2 t3 t0 t internal _ dly t shutter _ dly t pchg shutter close t datout_dly vsync sccb strobe out frex out shutter 4689_ds_4_20 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 table 4-12 frex strobe control registers (sheet 1 of 3) address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[3]: start_point_selection bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128 (2^gain) (step+1) tsclk 0x37c5 frex reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2 exposure time in units of 128 system clock cycles 0x37c6 frex reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c9 frex reg9 0x00 rw bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-23 0x37cc frex regc 0x00 rw bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2 sensor precharge is in units of 1 system clock cycle. 0x37cf frex regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2 readout delay time is in units of 128 system clock cycles. 0x37d1 frex reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[4:0]: strobe delay[12:8] msb of strobe delay time strobe delay time is in units of 1 system clock cycles 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] lsb of strobe delay time 0x37de frex reg1e 0x01 rw bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 4-12 frex strobe control registers (sheet 2 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37df frex reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 4-12 frex strobe control registers (sheet 3 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 4-25 4.8.2.1 exposure time control registers: r_frame_exp = {0x37c5, 0x37c6, 0x37c7}, 24 bits, 1 step = 128 clock cycles. minimum exposure time: 0x37c5 = 0x00, 0x37c6 = 0x00, 0x37c7 = 0x00. if OV4689 works at 120 mhz, the minimum exposur e time is 0 and minimum step is 1.067 s. maximum exposure time: 0x37c5 = 0xff, 0x37c6 = 0xff, 0x37c7 = 0xff. if OV4689 works at 120 mhz, the maximum exposure time is 13.98 sec. 4.8.2.2 shutter delay control registers: r_shutter_dly = {0x37cc[4:0], 0x37c d[7:0]}, 13 bits, 1 step = 128 clock cycles. minimum shutter delay time: 0x37cc = 0x00, 0x37cd = 0x00. minimum step is 1.067 s. maximum shutter delay time: 0x37cc = 0x1f, 0x37cd = 0xff. if OV4689 works at 120 mhz, the maximum shutter delay time is 8.74 ms. 4.8.2.3 sensor pre charge control registers: r_frex_pchg = {0x37ce[7:0], 0x37cf[7:0]}, 16 bits, 1 step = 1 system clock cycle. these registers affect sensor performance. it is fo r internal use and not recommended for customer to change. 4.8.2.4 strobe control registers: r_strobe_width = {0x37c9[3:0], 0x37ca[ 7:0], 0x37cb[7:0]}, 20 bits, 1 step = 1 clock cycle. these registers control the strobe signal output width. register: r_strobe_dky = {0x37d2[4:0], 0x7d3[7:0]}, 13 bits, 1 step - 1 clock cycle. these registers control the delay between strobe to shutter. color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-1 5 image sensor proces sor digital functions 5.1 dsp top two functions of dsp top are to integrate all sub-modules and to create necessary control signals. table 5-1 dsp top registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[1]: average enable bit[0]: isp enable 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[4]: isp eof select bit[3]: isp sof select bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[3]: wb bias manual enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias manual enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x500a isp ctrl0a 0x00 rw bit[7:0]: x address end address 0x500b isp ctrl0b 0x00 rw bit[7:0]: y address end address 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x502a isp ctrl 2a 0x00 rw bit[0]: long add offset[8] 0x502b isp ctrl 2b 0x00 rw bit[7:0]: long add offset[7:0] 0x502c isp ctrl 2c 0x00 rw bit[0]: middle add offset[8] 0x502d isp ctrl 2d 0x00 rw bit[7:0]: middle add offset[7:0] 0x502e isp ctrl 2e 0x00 rw bit[0]: short add offset[8] 0x502f isp ctrl 2f 0x00 rw bit[7:0]: short add offset[7:0] 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1]: debug mode table 5-1 dsp top registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-3 5.2 dsp_pre the main purposes of the dsp_pre module include: ? adjust href, valid, rblue signals and data ? create color bar image ? determine the sizes of input image by removing redundant data ? create control signals table 5-2 pre_isp registers (sheet 1 of 2) address register name default value r/w description 0x5040 pre isp test ctrl 0x00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x5050~ 0x5051 debug mode ? ? debug mode 0x504c pre isp pix num ? r bit[7:0]: pixel_number_h[15:8] 0x504d pre isp pix num ? r bit[7:0]: pixel_number_l[7:0] 0x504e pre isp ln num ? r bit[7:0]: line_number_h[15:8] 0x504f pre isp ln num ? r bit[7:0]: line_number_l[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5057 pre isp xy inc ? r bit[7:4]: x_odd_inc bit[3:0]: y_odd_inc 0x5058 pre isp x off r ? r bit[7:0]: x_offset[15:8] 0x5059 pre isp x off r ? r bit[7:0]: x_offset[7:0] 0x505a pre isp y off r ? r bit[7:0]: y_offset[15:8] 0x505b pre isp y off r ? r bit[7:0]: y_offset[7:0] 0x505c pre isp win x off ? r bit[7:0]: win_x_offset[15:8] 0x505d pre isp win x off ? r bit[7:0]: win_x_offset[7:0] 0x505e pre isp win y off ? r bit[7:0]: win_y_offset[15:8] 0x505f pre isp win y off ? r bit[7:0]: win_y_offset[7:0] 0x5060 pre isp win x out ? r bit[7:0]: win_x_output_h size[15:8] 0 x5061 pre isp win x out ? r bit[7:0]: win_x_output_l size[7:0] 0x5062 pre isp win y out ? r bit[7:0]: win_y_output_h size[15:8] 0x5063 pre isp win y out ? r bit[7:0]: win_y_output_l size[7:0] 0x5064 pre isp skip ? r bit[5:4]: x_skip bit[1:0]: y_skip 0x5065 pre isp ctrl 25 ? r bit[7:4]: x even inc bit[3:0]: y even inc 0x5066 pre isp ctrl 26 ? r bit[3]: x odd inc[4] bit[2]: y odd inc[4] bit[1]: x even inc[4] bit[0]: y even inc[4] 0x5067 pre isp ctrl 27 ? r bit[2:0]: y cut top offset[10:8] 0x5068 pre isp ctrl 28 ? r bit[7:0]: y cut top offset[7:0] 0x5069 pre isp ctrl 29 ? r bit[2:0]: y cut bottom offset[10:8] 0x506a pre isp ctrl 2a ? r bit[7:0]: y cut bottom offset[7:0] 0x506b pre isp ctrl 2b 0x06 rw bit[2:0]: y address fullsize[10:8] 0x506c pre isp ctrl 2c 0x00 rw bit[7:0]: y address fullsize[7:0] table 5-2 pre_isp registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-5 5.3 otp for cluster cancellation table 5-3 otp for cluster cancellation registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor exposure constrain enable bit[0]: sensor gain constrain enable 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expo constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp expo constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.4 window control (winc) the main purpose of the winc module is to make t he image size to be real size by removing offset. 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7 :0]: otp expo constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 5-4 winc registers address register name default value r/w description 0x5980 win xstart_off 0x 00 rw bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x 00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x 00 rw bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x 00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[4:0]: window width[12:8] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[0]: window size manual 0: disable 1: enable 0x5989 win px_cnt ? r bit[4:0]: pixel counter[12:8] 0x598a win px_cnt ? r bit[7:0]: pixel counter[7:0] 0x598b win ln_cnt ? r bit[3:0]: line counter[11:8] 0x598c win ln_cnt ? r bit[7:0]: line counter[7:0] table 5-3 otp for cluster cancellation registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 5-7 5.5 manual white balance (mwb) the mwb provides digital gain for r,g and b channels. each channel gain is 12 -bit. 0x400 is 1x gain. table 5-5 mwb registers address register name default value r/w description 0x500c isp ctrl0c 0x04 rw bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] 0x5018 isp ctrl 18 0x04 rw bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 5.6 avg the main function of the avg module is to calc ulate the luminance average using special filters. table 5-6 avg control registers address register name default value r/w description 0x5680 avg x start 0x00 rw bit[3:0]: x start offset[11:8] 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] 0x5682 avg y start 0x00 rw bit[3:0]: y start offset[11:8] 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] 0x5684 avg win width 0x0a rw bit[3:0]: window width[11:8] 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] 0x5686 avg win height 0x05 rw bit[3:0]: window height[11:8] 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[1]: average option 0: sum=(4*b+9*g*2+10*r) /8 1: sum=b+g*2+r bit[0]: average size manual 0: disable 1: enable 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-1 6 register tables the following tables provide descriptions of the device control registers contai ned in the OV4689. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x6c for write and 0x6d for read (when sid=1, 0x20 for write and 0x21 for read). 6.1 pll control [0x0300 ~ 0x031f] table 6-1 pll registers (sheet 1 of 3) address register name default value r/w description 0x0300 pll_ctrl_0 0x00 rw bit[7:3]: debug mode bit[2:0]: pll1_pre_div 0x0301 pll_ctrl_1 0x00 rw bit[7:2]: debug mode bit[1:0]: pll1_multiplier[9:8] 0x0302 pll_ctrl_2 0x2a rw bit[7:0]: pll1_multiplier[7:0] 0x0303 pll_ctrl_3 0x00 rw bit[7:4]: debug mode bit[3:0]: pll1_divm divider = /(1+ pll1_divm) (range from /1~16) 0x0304 pll_ctrl_4 0x03 rw bit[7:2]: debug mode bit[1:0]: pll1_div_mipi 00: /4 01: /5 10: /6 11: /8 0x0305 pll_ctrl_5 0x01 rw bit[7:2]: debug mode bit[1:0]: pll1_div_sp 00: /3 01: /4 10: /5 11: /6 0x0306 pll_ctrl_6 0x01 rw bit[7:1]: debug mode bit[0]: pll1_div_s 0: /1 1: /2 0x0307 debug mode ? ? debug mode 0x0308 pll_ctrl_8 0x00 rw bit[7:1]: debug mode bit[0]: pll1_bypass 0x0309 pll_ctrl_9 0x01 rw bit[7:3]: debug mode bit[2:0]: pll1_cp color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x030a pll_ctrl_a 0x00 rw bit[7:1]: debug mode bit[0]: pll1_predivp 0: /1 1: /2 0x030b pll_ctrl_b 0x00 rw bit[7:3]: debug mode bit[2:0]: pll2_pre_div 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /4 110: /6 111: /8 0x030c pll_ctrl_c 0x00 rw bit[7:2]: debug mode bit[1:0]: pll2_multiplier[9:8] 0x030d pll_ctrl_d 0x1e rw bit[7:0]: pll2_multiplier[7:0] 0x030e pll_ctrl_e 0x04 rw bit[7:3]: debug mode bit[2:0]: pll2_rdivs 000: /1 001: /1.5 010: /2 011: /2.5 100: /3 101: /3.5 110: /4 111: /5 0x030f pll_ctrl_f 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divsp divider = /(1+ pll2_divsp) (range from /1~16) 0x0310 pll_ctrl_10 0x01 rw bit[7:3]: debug mode bit[2:0]: pll2_cp 0x0311 pll_ctrl_11 0x00 rw bit[7:1]: debug mode bit[0]: pll2_bypass 0x0312 pll_ctrl_12 0x01 rw bit[7:4]: debug mode bit[3:0]: pll2_divdac divider = /(1+ pll2_divdac) (range from /1~16) 0x031b pll_ctrl_1b 0x00 rw bit[7:1]: debug mode bit[0]: pll1_rst 0x031c pll_ctrl_1c 0x00 rw bit[7:1]: debug mode bit[0]: pll2_rst table 6-1 pll registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-3 6.2 system control (sc) [0x0100 ~ 0x303f] 0x031e debug mode ? ? debug mode 0x031f pll_ctrl_1f 0x00 rw bit[7:2]: debug mode bit[1:0]: lvds_bit_sel 00: bit[8] others: bit[10] table 6-2 sc registers (sheet 1 of 6) address register name default value r/w description 0x0100 sc_ctrl0100 0x00 rw bit[7:1]: debug mode bit[0]: software_standby 0: software_standby 1: streaming 0x0103 sc_ctrl0103 0x00 rw bit[7:1]: debug mode bit[0]: software_reset 0x3000 sc_cmmn_pad_ oen0 0x00 rw bit[7:6]: not used bit[5]: fsin output enable 0: input 1: output bit[4:0]: debug mode 0x3001 debug mode ? ? debug mode 0x3002 sc_cmmn_pad_ oen2 0x20 rw bit[7]: vsync output enable 0: input 1: output bit[6]: href output enable 0: input 1: output bit[5]: debug mode bit[4]: frex output enable 0: input 1: output bit[3:1]: debug mode bit[0]: gpio0 output enable 0: input 1: output 0x3004 sccb id 0x6c rw sccb slave id1 table 6-1 pll registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3005 sc_cmmn_clkrst5 0xf0 rw bit[7:6]: debug mode bit[5]: enable src clock bit[4]: enable sync fifo clock bit[3:2]: debug mode bit[1]: reset src bit[0]: reset sync fifo 0x3006 cmmn_sccb_id2 0x42 rw sccb slave id, sensor unique id not related to sid control 0x3007 core_ctrl2 0x38 rw bit[7]: pll12_dacclk_sel bit[6]: r_fc_byp bit[5]: ispin_array_addr_sel bit[4:0]: debug mode 0x3008 sc_cmmn_pad_ out0 0x00 rw register control output pad output as gpio (works only when related bits in register 0x300e are set to 1) bit[7:0]: debug mode 0x3009 debug mode ? ? debug mode 0x300a sc_cmmn_chip_id 0x46 r chip id high 0x300b sc_cmmn_chip_id 0x88 r chip id low 0x300d sc_cmmn_pad_ out2 0x00 rw register control output pad output as gpio (works only when related bits in register 0x3010 are set to 1) bit[7]: register control vsync output bit[6]: register control href output bit[5]: not used bit[4]: register control frex output bit[3]: register control strobe output bit[2]: register control siod output bit[1]: register control il_pwm output bit[0]: register control gpio output 0x300e~ 0x300f debug mode ? ? debug mode table 6-2 sc registers (sheet 2 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-5 0x3010 sc_cmmn_pad_ sel2 0x00 rw enable pad as gpio controlled by registers (0: pad by data path control; 1: pad as gpio controlled by register) bit[7]: enable vsync as gpio controlled by register bit[6]: enable href as gpio controlled by register bit[5]: enable sif_sda as gpio controlled by register bit[4]: enable frex as gpio controlled by register bit[3]: enable strobe as gpio controlled by register bit[2]: enable sccb_sda as gpio controlled by register bit[1:0]: debug mode 0x3011 sc_cmmn_pad_pk 0x00 rw bit[7]: not used bit[6:5]: pad_driving_strength 00: 1x 01: 2x 10: 3x 11: 4x bit[2]: fsin_pad_enb bit[1]: frex_pad_enb bit[0]: not used 0x3012 sccb_second_id 0x20 rw sccb slave id2 0x3016 sc_cmmn_mipi_pk 0x08 rw not used 0x3017 sc_cmmn_mipi_pk 0x10 rw not used 0x3018 sc_cmmn_mipi_sc_ ctrl 0x72 rw bit[7:5] mipi lane mode 000: 1-lane mode 001: 2-lane mode 011: 4-lane mode others: not allowed bit[4]: debug mode bit[3]: not used bit[2]: pd_mipi_manual bit[1]: reset mipi phy when sleep bit[0]: auto disable mipi lane when sleep table 6-2 sc registers (sheet 3 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3019 sc_cmmn_mipi_sc_ ctrl 0x00 rw bit[7:4]: debug mode bit[3]: manual lane disable 1: disable mipi lane 3 bit[2]: manual lane disable 1: disable mipi lane 2 bit[1]: manual lane disable 1: disable mipi lane 1 bit[0]: manual lane disable 1: disable mipi lane 0 0x301a sc_cmmn_clkrst0 0xf0 rw bit[7]: enable emb clock bit[6]: enable strobe clock bit[5]: debug mode bit[4]: enable timing control clock bit[3]: mipi_phy_rst_manual bit[2]: reset strobe block bit[1]: reset analog control block bit[0]: reset timing control block 0x301b sc_cmmn_clkrst1 0xf0 rw bit[7]: enable blc clock bit[6]: enable isp clock bit[5]: enable avg clock bit[4]: enable vfifo clock bit[3]: reset blc bit[2]: reset isp bit[1]: reset testmod bit[0]: reset vfifo 0x301c sc_cmmn_clkrst2 0xf0 rw bit[7]: debug mode bit[6]: enable mipi clock bit[5]: debug mode bit[4]: enable otp clock bit[3]: debug mode bit[2]: reset mipi bit[1]: debug mode bit[0]: reset otp 0x301d sc_cmmn_clkrst3 0xf0 rw bit[7]: debug mode bit[6]: enable group control clock bit[5]: enable bist clock bit[4:3]: debug mode bit[2]: reset group control bit[1]: reset bist bit[0]: debug mode table 6-2 sc registers (sheet 4 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-7 0x301e sc_cmmn_clkrst4 0xf0 rw bit[7]: debug mode bit[6]: pclk_lvds bit[5]: pclk_vfifo bit[4]: pclk_mipi bit[3]: debug bit[2]: rst_lvds bit[1]: rst_emb bit[0]: debug mode 0x301f sc_cmmn_clkrst5 0x00 rw reset each module before entering into frex mode bit[7]: reset aec bit[6]: reset src/blc/sync_fifo bit[5]: reset isp bit[4]: debug mode bit[3]: reset mipi bit[2]: reset vfifo bit[1]: reset testmod bit[0]: reset mipi_phy 0x3020 sc_cmmn_clock_ sel 0x93 rw bit[7]: clock switch control 0: switch to pad clock 1: switch to pll clock bit[6:4]: debug mode bit[3]: pclk_sel 0: select pll_pclk_i 1: select pll_pclk_d2 bit[2:0]: debug mode 0x3021 sc_cmmn_misc_ ctrl 0x63 rw bit[7]: debug mode bit[6]: sleep no latch enable bit[5]: fst_stby_ctr 0: software standby enter at v_blk 1: software standby enter at l_blk bit[4:1]: debug mode bit[0]: cen_global_o for all sram 0x3022 sc_cmmn_mipi_sc_ ctrl 0x01 rw bit[7:4]: debug mode bit[3]: enable lvds mode bit[2]: mipi clock lane1 disable manual bit[1]: mipi clock lane0 disable manual bit[0]: enable power down mipi when sleep 0x302a sc_cmmn_sub_id ? r bit[7:4]: process bit[3:0]: version table 6-2 sc registers (sheet 5 of 6) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.3 sccb control [0x3100 ~ 0x3106] 0x3030 sc_cmmn_clk_inv 0x00 rw bit[7:6]: debug mode bit[5]: reverse sclk bit[4]: reverse pclk bit[3:0]: debug mode 0x3031 sc_cmmn_bit_sel 0x0a rw bit[7:5]: debug mode bit[4:0]: mipi_bit_sel 01000: 8-bit mode 01010: 10-bit mode 01100: 12-bit mode others: not allowed 0x3032 sc_cmmn_core_ ctrl0 0x00 rw bit[7]: isp_sof_in_opt bit[6]: debug mode bit[5]: array_hskip_man_en bit[4]: sram_bin_man_en bit[3]: sram_hbin_man bit[2:0]: array_hskip_man[3:1] 0x3034~ 0x3036 debug mode ? ? debug mode 0x3037 sid ctrl 0x00 rw bit[7:1]: debug mode bit[0]: r_sid 0: select id1 when sid = 0 or id2 when sid = 1 1: select id2 when sid = 0 or id1 when sid = 1 0x3038~ 0x303d debug mode ? ? debug mode 0x303f sccb_id_ctrl 0x00 rw bit[7:1]: debug mode bit[0]: enable programmable id1 and id2 0: id1 fix = 0x6c id2 fix = 0x20 1: id1 from register 0x3004 id2 from register 0x3012 table 6-3 sccb registers address register name default value r/w description 0x3100~ 0x3106 debug mode ? ? debug mode table 6-2 sc registers (sheet 6 of 6) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-9 6.4 group hold [0x3200 ~ 0x320f] table 6-4 group hold registers (sheet 1 of 2) address register name default value r/w description 0x3200 group adr0 0x 00 rw group0 start address in sram, actual address is {0x3200[5:0], 0x0} 0x3201 group adr1 0x10 rw group1 start address in sram, actual address is {0x3201[5:0], 0x0} 0x3202 group adr2 0x20 rw group2 start address in sram, actual address is {0x3202[5:0], 0x0} 0x3203 group adr3 0x30 rw group3 start address in sram, actual address is {0x3203[5:0], 0x0} 0x3204 group len0 ? r length of group0 0x3205 group len1 ? r length of group1 0x3206 group len2 ? r length of group2 0x3207 group len3 ? r length of group3 0x3208 group access ? w bit[7:4]: group_ctrl 0000: group hold start 0001: group hold end 1010: group launch 1110: fast group launch others: debug mode bit[3:0]: group id 0000: group bank 0 0001: group bank 1 0010: group bank 2 0011: group bank 3 others: debug mode 0x3209 group0 period 0x00 rw bit[7]: debug mode bit[6:5]: switch back group bit[4:0]: number of frames to stay in group 0 0x320a group1 period 0x00 rw number of frames to stay in group 1 0x320b grp_sw_ctrl 0x01 rw bit[7]: auto switch enable bit[6:5]: debug mode bit[4]: frame_cnt_trig bit[3]: group_switch_repeat enable the first group (group 0) and second group repeatable switch bit[2]: context_en enable the switch from second group back to first group (group 0) bit[1:0]: second group select color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.5 asram control [0x3300 ~ 0x3318] 6.6 adc and analog control [0x3600 ~ 0x364c] 6.7 sensor control [0x3700 ~ 0x379a] 0x320c sram test 0x0a rw bit[7:5]: debug mode bit[4]: group hold sram test enable bit[3:0]: group hold sram rm[3:0] 0x320d grp_act ? r active group indicator 0x320e fm_cnt_grp0 ? r group 0 frame count 0x320f fm_cnt_grp1 ? r group 1 frame count table 6-5 asram control registers address register name default value r/w description 0x3300~ 0x3318 asram test ? ? asram control registers table 6-6 adc and analog control registers address register name default value r/w description 0x3600~ 0x364c analog ctrl ? ? analog control registers table 6-7 sensor control registers (sheet 1 of 2) address register name default value r/w description 0x3700~ 0x375f sensor ctrl ? ? sensor timing control registers table 6-4 group hold registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-11 6.8 frex control [0x37c5 ~ 0x37df] 0x3760 sensor ctrl60 0x00 rw max medium exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3761 sensor ctrl61 0x00 rw max medium exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3762 sensor ctrl62 0x00 rw max short exposure time in staggered hdr mode msb (works only when 0x3764[0] = 1) 0x3763 sensor ctrl63 0x00 rw max short exposure time in staggered hdr mode lsb (works only when 0x3764[0] = 1) 0x3764 sensor ctrl64 0x00 rw bit[0]: stagger hdr mode output timing manual control enable 0x3765~ 0x379c sensor ctrl ? ? sensor timing control registers table 6-8 frex control registers (sheet 1 of 3) address register name default value r/w description 0x37c5 frex_reg5 0x00 rw bit[7:0]: frame exposure[23:16] msb of frame exposure time in mode 2. exposure time in units of 128 system clock cycles 0x37c6 frex_reg6 0x00 rw bit[7:0]: frame exposure[15:8] middle byte of frame exposure time in mode 2 0x37c7 frex_reg7 0x08 rw bit[7:0]: frame exposure[7:0] lsb of frame exposure time in mode 2 0x37c8 debug mode ? ? debug mode 0x37c9 frex_reg9 0x00 rw bit[7:4]: debug mode bit[3:0]: strobe width[19:16] msb of strobe width in mode 2. strobe width in units of 1 system clock cycle. 0x37ca frex_rega 0x06 rw bit[7:0]: strobe width[15:8] middle byte of strobe width in mode 2 0x37cb frex_regb 0x00 rw bit[7:0]: strobe width[7:0] lsb of strobe width in mode 2 table 6-7 sensor control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x37cc frex_regc 0x00 rw bit[7:5]: debug mode bit[4:0]: shutter dly[12:8] msb of shutter delay in mode 2. shutter delay is in units of 128 system clock cycles. 0x37cd frex_regd 0x44 rw bit[7:0]: shutter dly[7:0] lsb of shutter delay in mode 2 0x37ce frex_rege 0x1f rw bit[7:0]: frex precharge width[15:8] msb of sensor precharge in mode 2. sensor precharge is in units of 1 system clock cycle. 0x37cf frex_regf 0x40 rw bit[7:0]: frex precharge width[7:0] lsb of sensor precharge in mode 2 0x37d0 frex_reg10 0x00 rw bit[7:0]: readout delay[15:8] msb of readout delay time in mode 2. readout delay time is in units of 128 system clock cycles. 0x37d1 frex_reg11 0x01 rw bit[7:0]: readout delay[7:0] lsb of readout delay time in mode 2 0x37d2 frex_reg12 0x00 rw bit[7:5]: debug mode bit[4:0]: strobe delay[12:8] unit is system clock 0x37d3 frex_reg13 0x00 rw bit[7:0]: strobe delay[7:0] 0x37d4~ 0x37d6 debug mode ? ? debug mode 0x37de frex_reg1e 0x01 rw bit[7:1]: debug mode bit[0]: frex sccb request repeat trigger selection 0: sof 1: eof table 6-8 frex control registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-13 6.9 timing control [0x3800 ~ 0x3847] 0x37df frex_reg1f 0x04 rw bit[7]: frex sccb request (self-clearing) bit[6]: debug mode bit[5]: frex_strobe_out_sel 0: strobe for rolling mode 1: strobe for frame mode bit[4]: frex nopchg bit[3]: frex strobe polarity 0: active high 1: active low bit[2]: frex shutter polarity bit[1]: frex pad input enable 0: frame mode is triggered by register 1: frame mode is triggered by frex pad bit[0]: no latch at sof for frex sccb request 0: trigger frame mode in sof 1: trigger frame mode immediately table 6-9 timing control registers (sheet 1 of 4) address register name default value r/w description 0x3800 h_crop_start 0x00 rw bit[7:5]: debug mode bit[4:0]: horizontal crop start address[12:8] 0x3801 h_crop_start 0x00 rw bit[7:0]: horizontal crop start address[7:0] 0x3802 v_crop_start 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical crop start address[11:8] 0x3803 v_crop_start 0x04 rw bit[7:0]: vertical crop start address[7:0] 0x3804 h_crop_end 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal crop end address[12:8] 0x3805 h_crop_end 0x9f rw bit[7:0]: horizontal crop end address[7:0] 0x3806 v_crop_end 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical crop end address[11:8] 0x3807 v_crop_end 0xfb rw bit[7:0]: vertical crop end address[7:0] 0x3808 h_ourput_size 0x0a rw bit[7:5]: debug mode bit[4:0]: horizontal output size[12:8] table 6-8 frex control registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3809 h_output_size 0x80 rw bit[7:0]: horizontal output size[7:0] 0x380a v_ourput_size 0x05 rw bit[7:4]: debug mode bit[3:0]: vertical output size[11:8] 0x380b v_output_size 0xf0 rw bit[7:0]: vertical output size[7:0] 0x380c timing_hts 0x03 rw bit[7]: debug mode bit[6:0]: horizontal total size[14:8] 0x380d timing_hts 0x5c rw bit[7:0]: horizontal total size[7:0] 0x380e timing_vts 0x06 rw bit[7]: debug mode bit[6:0]: vertical total size[14:8] 0x380f timing_vts 0x10 rw bit[7:0]: vertical total size[7:0] 0x3810 h_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: horizontal windowing offset[11:8] 0x3811 h_win_off 0x10 rw bit[7:0]: horizontal windowing offset[7:0] 0x3812 v_win_off 0x00 rw bit[7:4]: debug mode bit[3:0]: vertical windowing offset[11:8] 0x3813 v_win_off 0x02 rw bit[7:0]: vertical windowing offset[7:0] 0x3814 h_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample odd increase number 0x3815 h_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: horizontal sub-sample even increase number 0x3816 vsync_start_h 0x00 rw bit[7:0]: timing control vsync start point[15:8] 0x3817 vsync_start_l 0x00 rw bit[7:0]: timing control vsync start point[7:0] 0x3818 vsync_end_h 0x00 rw bit[7:0]: timing control vsync end point[15:8] 0x3819 vsync_end_l 0x00 rw bit[7:0]: timing control vsync end point[7:0] 0x381a vts_exp_diff 0x04 rw bit[7:0]: difference between vts and exposure table 6-9 timing control registers (sheet 2 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-15 0x3820 format 0x00 rw timing control register bit[7:4]: debug mode bit[3]: bypass_isp bit[2]: digital vertical flip enable 0: normal 1: vertical flip bit[1]: array vertical flip enable 0: normal 1: vertical flip bit[0]: vbin 0x3821 format 0x00 rw bit[7:3]: debug mode bit[2]: digital horizontal mirror enable 0: normal 1: horizontal mirror bit[1]: array horizontal mirror enable 0: normal 1: horizontal mirror bit[0]: not used 0x3822 timing_reg22 0x88 rw bit[7:5]: zero_line_num /2 bit[4:0]: blc_line_num /2 0x3823 timing_reg23 0x00 rw bit[7]: ext_vs_re bit[6]: ext_vs_en bit[5:0]: debug mode 0x3824 cs_rst_fsin 0x00 rw bit[7:0]: cs reset value at vs_ext[15:8] 0x3825 cs_rst_fsin 0x20 rw bit[7:0]: cs reset value at vs_ext[7:0] 0x3826 r_rst_fsin 0x00 rw bit[7:0]: r reset value at vs_ext[15:8] 0x3827 r_rst_fsin 0x04 rw bit[7:0]: r reset value at vs_ext[7:0] 0x3828 timing_reg28 0x00 rw bit[7]: ext_hs_re bit[6]: ext_hs_en bit[5]: debug mode bit[4]: hts_inc_en at slave mode bit[3:0]: debug mode 0x3829 format 0x00 rw bit[7:4]: debug mode bit[3]: hdr_lite_en bit[2:0]: not used 0x382a v_inc_odd 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample odd increase number 0x382b v_inc_even 0x01 rw bit[7:5]: debug mode bit[4:0]: vertical sub-sample even increase number 0x382c blc_col_st 0x00 rw bit[7:0]: black column start address table 6-9 timing control registers (sheet 3 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x382d blc_col_end 0x7f rw bit[7:0]: black column end address 0x3830 blc_num_option 0x04 rw bit[7:5]: blc_adj bit[4:0]: blc_use_num /2 0x3831 blc_num_man 0x00 rw bit[7:6]: debug mode bit[5]: manually set blc num enable bit[4:0]: blc_num_man /2 0x3832 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[15:8] 0x3833 fractional_hts 0x00 rw bit[7:0]: fr actional hts in slave mode[7:0] 0x3834 ext_div_factors 0x01 rw bit[7:4]: ext_vs_div bit[3:0]: ext_hs_div 0x3835 debug mode ? ? debug mode 0x3836 timing_reg_36 0x01 rw bit[7:5]: debug mode bit[4:0]: r_zline_use_num/2 0x3837 timing_reg_37 0x00 rw bit[7]: stg_vc_man_en bit[6]: not used bit[5:4]: vc_l bit[3:2]: vc_m bit[1:0]: vc_s 0x3841 timing_reg_41 0x02 rw bit[7:5]: debug mode bit[4]: r_sdg_hdr_num bit[3:2]: debug mode bit[1]: r_rcnt_fix bit[0]: r_stg_hdr_en 0x3846 timing_reg_46 0x08 rw bit[7:5]: debug mode bit[4]: r_seq_hdr_sw_opt bit[3]: fcnt_trig_rst_en bit[2:0]: r_seq_hdr_num 0x3847 debug mode ? ? debug mode table 6-9 timing control registers (sheet 4 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-17 6.10 strobe [0x3b00 ~ 0x3b05] 6.11 psram control [0x3f00 ~ 0x3f0a] table 6-10 strobe control registers address register name default value r/w description 0x3b00 strobe ctrl 0x00 rw bit[7]: strobe on/off bit[6]: strobe polarity 0: active high 1: active low bit[5:4]: width_in_xenon bit[2:0]: mode 000: xenon 001: led1 010: led2 011: led3 100: led4 0x3b02 strobe dmy h 0x00 rw dummy lines added at strobe mode, msb 0x3b03 strobe dmy l 0x00 rw dummy lines added at strobe mode, lsb 0x3b04 strobe ctrl 0x00 rw bit[7:4]: debug mode bit[3]: start_point_sel bit[2]: strobe repeat enable bit[1:0]: strobe latency 00: strobe generated at next frame 01: strobe generated 2 frames later 10: strobe generated 3 frames later 11: strobe generated 4 frames later 0x3b05 strobe width 0x00 rw bit[7:2]: strobe pulse width step bit[1:0]: strobe pulse width gain strobe_pulse_width = 128(2^gain)(step+1)tsclk table 6-11 psram control registers address register name default value r/w description 0x3f00~ 0x3f0a psram ctrl ? ? psram control registers color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.12 adc sync control [0x4500 ~ 0x4503] 6.13 test mode [0x8000 ~ 0x8008] table 6-12 adc sync control registers address register name default value r/w description 0x4500~ 0x4503 adc_sync_ctrl ? ? adc sync control table 6-13 test mode registers address register name default value r/w description 0x8000 test ctrl1 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_b[11:8] 0x8001 test ctrl2 0x00 rw bit[7:0]: fix_pattern_b[7:0] 0x8002 test ctrl3 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gb[11:8] 0x8003 test ctrl4 0x00 rw bit[7:0]: fix_pattern_gb[7:0] 0x8004 test ctrl5 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_gr[11:8] 0x8005 test ctrl6 0x00 rw bit[7:0]: fix_pattern_gr[7:0] 0x8006 test ctrl7 0x00 rw bit[7:4]: debug mode bit[3:0]: fix_pattern_r[11:8] 0x8007 test ctrl8 0x00 rw bit[7:0]: fix_pattern_r[7:0] 0x8008 test ctrl9 0x00 rw bit[7:2]: debug mode bit[1]: pn9 enable bit[0]: fix pattern enable 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-19 6.14 otp control [0x3d80 ~ 0x3d8d] table 6-14 otp control registers (sheet 1 of 2) address register name default value r/w description 0x3d80 otp_program_ctrl 0x00 rw bit[7]: otp_wr_busy bit[6:1]: debug mode bit[0]: otp_program_enable 0x3d81 otp_loa_ctrl 0x00 rw bit[7]: otp_rd_busy bit[6]: debug mode bit[5]: otp_bist_error bit[4]: otp_bist_done bit[3:1]: debug mode bit[0]: otp_load_enable 0x3d82 otp_pgm_pulse 0x55 rw program strobe pulse width unit: 8system clock period 0x3d83 otp_load_pulse 0x08 rw load strobe pulse width unit: system clock period 0x3d84 otp_mode_ctrl 0x00 rw bit[7]: program disable 0: enable 1: disable bit[6]: mode select 0: auto mode 1: manual mode bit[5:0]: debug mode 0x3d85 otp_reg85 0x10 rw bit[7:6]: debug mode bit[5]: otp_bist_select 0: compare with sram 1: compare with zero bit[4]: otp_bist_enable bit[3]: debug mode bit[2]: otp power up load data enable bit[1]: otp power up load setting enable bit[0]: otp write register load setting enable 0x3d86 sram_test_signals 0x02 rw bit[7:3]: debug mode bit[2]: r_test bit[1:0]: r_rm 0x3d87 otp_ps2cs 0x0a rw otp ps to csb delay unit: system clock period 0x3d88 otp_start_address 0x00 rw otp start high address for manual mode 0x3d89 otp_start_address 0x00 rw otp start low address for manual mode color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.15 frame control [0x4200 ~ 0x4203] 0x3d8a otp_en_address 0x00 rw otp end high address for manual mode 0x3d8b otp_end_address 0x00 rw otp end low address for manual mode 0x3d8c otp_setting_stt_ address 0x00 rw otp start high address for load setting 0x3d8d otp_setting_stt_ address 0x00 rw otp start low address for load setting table 6-15 frame control registers address register name default value r/w description 0x4200 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4201 frame on number 0x00 rw bit[3:0]: frame on number 0x4202 frame off number 0x00 rw bit[3:0]: frame off number 0x4203 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-14 otp control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-21 6.16 ispfc [0x4240 ~ 0x4243] 6.17 format clip [0x4302 ~ 0x4307] table 6-16 ispfc registers address register name default value r/w description 0x4240 frame ctrl0 0x00 rw bit[7:3]: debug mode bit[2]: fcnt_eof_sel bit[1]: fcnt_mask_dis bit[0]: fcnt_reset 0x4241 frame on number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame on number 0x4242 frame off number 0x00 rw bit[7:4]: debug mode bit[3:0]: frame off number 0x4243 frame ctrl1 0x00 rw bit[7:6]: debug mode bit[5]: data_mask_dis bit[4]: valid_mask_dis bit[3]: href_mask_dis bit[2]: eof_mask_dis bit[1]: sof_mask_dis bit[0]: all_mask_dis table 6-17 format clip registers address register name default value r/w description 0x4302 clipping max 0xff rw bit[7:0]: clipping max[15:8] 0x4303 clipping max 0xff rw bit[7:0]: clipping max[7:0] 0x4304 clipping min 0x00 rw bit[7:0]: clipping min[15:8] 0x4305 clipping min 0x00 rw bit[7:0]: clipping min[7:0] 0x4306 dpcm_ctrl 0x00 rw bit[7:3]: debug mode bit[2]: vfifo_pix_swap bit[1]: dpcm_en bit[0]: vfifo_rblue 0: first is red line 1: first is blue line 0x4307 mipi dt16 0x2e rw bit[7:0]: debug mode 0x4308 embed ctrl 0x02 rw bit[7:1]: debug mode bit[0]: embed_en color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.18 vfifo [0x4600 ~ 0x4603] 6.19 mipi top [0x4800 ~ 0x484f] table 6-18 vfifo registers address register name default value r/w description 0x4600 vfifo_ctrl_00 0x00 rw bit[7:0]: r_vfifo_read_start[15:8] 0x4601 vfifo_ctrl_01 0x04 rw bit[7:0]: r_vfifo_read_start[7:0] 0x4602~ 0x4603 debug mode ? ? debug mode table 6-19 mipi top registers (sheet 1 of 9) address register name default value r/w description 0x4800 mipi ctrl 00 0x04 rw mipi control 00 bit[7]: mipi_hs_only 1: mipi always in high speed mode bit[6]: debug mode bit[5]: clock lane gate enable 0: clock lane is free running 1: gate clock lane when no packet to transmit bit[4]: line sync enable 0: do not send line short packet for each line 1: send line short packet for each line bit[3]: r_frame_act_all1 bit[2:0]: debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-23 0x4801 mipi ctrl 01 0x00 rw mipi control 01 bit[7]: debug mode bit[6]: short packet data type manual enable 1: use dt_spkt as short packet data bit[5]: first_bit change clk_lane first bit 0: output 0x05 1: output 0xaa bit[4]: ph bit order for ecc 0: {di[7:0],wc[7:0], wc[15:8]} 1: {di[0:7],wc[0:7], wc[8:15]} bit[3:2]: debug mode bit[1]: lpx select for pclk domain 0: auto calculate t_lpx_p, unit pclk2x cycle 1: use lpx_p_min[7:0] bit[0]: debug mode table 6-19 mipi top registers (sheet 2 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4802 mipi ctrl 02 0x00 rw mipi control 02 bit[7]: hs_prepare_sel 0: auto calculate t_hs_prepare, unit pclk2x 1: use hs_prepare_min_o[7:0] bit[6]: clk_prepare_sel 0: auto calculate t_clk_prepare, unit pclk2x 1: use clk_prepare_min_o[7:0] bit[5]: clk_post_sel 0: auto calculate t_clk_post, unit pclk2x 1: use clk_post_min_o[7:0] bit[4]: clk_trail_sel 0: auto calculate t_clk_trail, unit pclk2x 1: use clk_trail_min_o[7:0] bit[3]: hs_exit_sel 0: auto calculate t_hs_exit, unit pclk2x 1: use hs_exit_min_o[7:0] bit[2]: hs_zero_sel 0: auto calculate t_hs_zero, unit pclk2x 1: use hs_zero_min_o[7:0] bit[1]: hs_trail_sel 0: auto calculate t_hs_trail, unit pclk2x 1: use hs_trail.min_o[7:0] bit[0]: clk_zero_sel 0: auto calculate t_clk_zero, unit pclk2x 1: use clk_zero_min_o[7:0] 0x4803 mipi ctrl 03 0x00 rw mipi control 03 bit[7:4]: debug mode bit[3]: manual_ofset_o t_period manual offset bit[2]: r_manual_half2one t_period half to 1 bit[1:0]: debug mode 0x4804 mipi ctrl 04 0x04 rw mipi control 04 bit[7:4]: man_lane_num bit[3]: lane_num_manual_enable bit[2]: lane4_6b_en 1: support 4,7,8-lane 6-bit bit[1:0]: debug mode table 6-19 mipi top registers (sheet 3 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-25 0x4805 mipi ctrl 05 0x00 rw mipi control 05 bit[7:4]: debug mode bit[3]: lpda_retime_manu_o bit[2]: lpda_retime_sel_o 1: manual bit[1]: lpck_retime_manu_o bit[0]: lpck_retime_sel_o 1: manual 0x4806 mipi reg r/w ctrl 0x10 rw bit[7:4]: debug mode bit[3]: mipi_remote_rst bit[2]: mipi_susp bit[1]: smia_lane_ch_en bit[0]: tx_lsb_first 0x4807 sw t lpx 0x03 rw bit[7:4]: debug mode bit[3:0]: ul_tx_lpx 0x4808 wkup dly 0x0a rw bit[7:0]: mark1 wake-up delay/2^10 0x4810 mipi max frame count 0xff rw high byte of maximum frame count of frame sync short packet 0x4811 mipi max frame count 0xff rw low byte of maximum frame count of frame sync short packet 0x4813 mipi ctrl13 0x00 rw mipi control 13 bit[7:4]: debug mode bit[3]: select hdr vi rtual channel enable 0: select manual input vc 1: select hdr vc bit[2]: vc_sel input vc or register vc bit[1:0]: vc virtual channel of mipi 0x4814 mipi ctrl14 0x2a rw mipi control 14 bit[7]: debug mode bit[6]: lpkt_dt_sel 0: use mipi_dt 1: use dt_man_o as long packet data bit[5:0]: data type in manual mode table 6-19 mipi top registers (sheet 4 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4815 mipi_dt_spkt 0x00 rw bit[7]: debug mode bit[6]: pclk_inv 0: use falling edge of mipi_pclk_o to generate mipi bus to phy 1: use rising edge of mipi_pclk_o to generate mipi bus to phy bit[5:0]: manual data type for short packet 0x4816 emb_dt_sel 0x52 rw emb_dt_sel bit[7]: debug mode bit[6]: emb_line_sel 1: use emb_dt as data in first emb_line_nu bit[5:0]: emb_dt manual set embedded data type 0x4818 hs_zero_min 0x00 rw high byte of minimum value for hs_zero, unit ns 0x4819 hs_zero_min 0x70 rw low byte of minimum value for hs_zero, unit ns hs_zero_real = hs_zero_min_o + tui*ui_hs_zero_min_o 0x481a hs_trail_min 0x00 rw high byte of minimum value for hs_trail, unit ns 0x481b hs_trail_min 0x3c rw low byte of minimum value for hs_trail, unit ns hs_trail_real = hs_trail_min_o + tui*ui_hs_trail_min_o 0x481c clk_zero_min 0x01 rw high byte of minimum value for clk_zero, unit ns 0x481d clk_zero_min 0x06 rw low byte of minimum value for clk_zero, unit ns clk_zero_real = clk_zero_min_o + tui*ui_clk_zero_min_o 0x481e clk_prepare_max 0x5f rw maximum value for clk_prepare, unit ns clk_prepare_max 0x481f clk_prepare_min 0x36 rw minimum value for clk_prepare clk_prepare_real = clk_prepare_min_o + tui*ui_clk_prepare_min_o 0x4820 clk_post_min 0x00 rw high byte of minimum value for clk_post, unit ns bit[7:2]: debug mode bit[1:0]: clk_post_min[9:8] 0x4821 clk_post_min 0x3c rw low byte of minimum value for clk_post, unit ns clk_post_real = clk_post_min_o + tui*ui_clk_post_min_o table 6-19 mipi top registers (sheet 5 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-27 0x4822 clk_trail_min 0x00 rw high byte of minimum value for clk_trail, unit ns bit[7:2]: debug mode bit[1:0]: clk_trail_min[9:8] 0x4823 clk_trail_min 0x3c rw low byte of minimum value for clk_trail, unit ns clk_trail_real = clk_trail_min_o + tui*ui_clk_trail_min_o 0x4824 lpx_p_min 0x00 rw high byte of minimum value for lpx_p, unit ns bit[7:2]: debug mode bit[1:0]: lpx_p_min[9:8] 0x4825 lpx_p_min 0x32 rw low byte of minimum value for lpx_p, unit ns lpx_p_real = lpx_p_min_o + tui*ui_lpx_p_min_o 0x4826 hs_prepare_min 0x28 rw minimum value for hs_prepare, unit ns hs_prepare_min 0x4827 hs_prepare_max 0x55 rw maximum value for hs_prepare hs_prepare_real = hs_prepare_min_o + tui*ui_hs_prepare_min_o 0x4828 hs_exit_min 0x00 rw high byte of minimum va lue for hs_exit, unit ns bit[7:2]: debug mode bit[1:0]: hs_exit_min[9:8] 0x4829 hs_exit_min 0x64 rw low byte of minimum value for hs_exit, unit ns hs_exit_real = hs_exit_min_o + tui*ui_hs_exit_min_o 0x482a ui_hs_zero_min 0x06 rw minimum ui value for hs_zero, unit ui 0x482b ui_hs_trail_min 0x04 rw minimum ui value for hs_trail, unit ui 0x482c ui_clk_zero_min 0x00 rw minimum ui value for clk_zero, unit ui 0x482d ui_clk_prepare 0x00 rw ui_clk_prepare_min_ctrl bit[7:4]: debug mode bit[3:0]: ui_clk_prepare_min minimum ui value of clk_prepare, unit ui 0x482e ui_clk_post_min 0x34 rw minimum ui value of clk_post, unit ui 0x482f ui_clk_trail_min 0x00 rw minimum ui value of clk_trail, unit ui 0x4830 ui_lpx_p_min 0x00 rw minimum ui value of lpx_p, unit ui table 6-19 mipi top registers (sheet 6 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4831 ui_hs_prepare_min 0x6c rw ui_hs_prepare bit[7:4]: ui_hs_prepare_max maximum ui value of hs_prepare, unit ui bit[3:0]: ui_hs_prepare_min minimum ui value of hs_prepare, unit ui 0x4832 ui_hs_exit_min 0x00 rw minimum ui value of hs_exit, unit ui 0x4833 mipi_pkt_st_size 0x08 rw bit[7:6]: debug mode bit[5:0]: mipi_pkt_start_size 0x4836 glb_mode_sel 0x00 rw glb_mode_sel bit[7:1]: debug mode bit[0]: smia_cal_en 0: use period to calculate 1: use smia bit rate to calculate 0x4837 pclk_period 0x08 rw period of pclk 2x, pclk_div = 1, and 1-bit decimal 0x4838 mipi_lp_gpio0 0x00 rw bit[7]: lp_sel0 0: auto generate mipi_lp_dir0_o 1: use lp_dir_man0 to be mipi_lp_dir0_o bit[6]: lp_dir_man0 0: input 1: output bit[5]: lp_p0_o bit[4]: lp_n0_o bit[3]: lp_sel1 0: auto generate mipi_lp_dir1_o 1: use lp_dir_man1 to be mipi_lp_dir1_o bit[2]: lp_dir_man1 0: input 1: output bit[1]: lp_p1_o bit[0]: lp_n1_o table 6-19 mipi top registers (sheet 7 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-29 0x4839 mipi_lp_gpio1 0x00 rw bit[7]: lp_sel2 0: auto generate mipi_lp_dir2_o 1: use lp_dir_man2 to be mipi_lp_dir2_o bit[6]: lp_dir_man2 0: input 1: output bit[5]: lp_p2_o bit[4]: lp_n2_o bit[3]: lp_sel3 0: auto generate mipi_lp_dir3_o 1: use lp_dir_man3 to be mipi_lp_dir3_o bit[2]: lp_dir_man3 0: input 1: output bit[1]: lp_p3_o bit[0]: lp_n3_o 0x483c mipi_ctrl3c 0x42 rw bit[7:4]: debug mode bit[3:0]: t_clk_pre unit: pclk2x cycle 0x483d mipi_lp_gpio4 0x00 rw bit[7]: lp_ck_sel0 0: auto generate mipi_ck_lp_dir0_o 1: use lp_ck_dir_man0 to be mipi_ck_lp_dir0_o bit[6]: lp_ck_dir_man0 0: input 1: output bit[5]: lp_ck_p0_o bit[4]: lp_ck_n0_o bit[3]: lp_ck_sel1 0: auto generate mipi_ck_lp_dir1_o 1: use lp_ck_dir_man1 to be mipi_ck_lp_dir1_o bit[2]: lp_ck_dir_man1 0: input 1: output bit[1]: lp_ck_p1_o bit[0]: lp_ck_n1_o table 6-19 mipi top registers (sheet 8 of 9) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x484a sel_mipi_ctrl4a 0x07 rw bit[7:6]: debug mode bit[5]: slp_lp_pon_man_o set for power up bit[3]: slp_lp_pon_da bit[3]: slp_lp_pon_ck bit[2]: mipi_slp_man_st mipi bus status manual control enable in sleep mode bit[1]: clk_lane_state bit[0]: data_lane_state 0x484b smia_option 0x07 rw bit[7:3]: debug mode bit[2]: line_st_sel_o 0: line start after href 1: line start after fifo_st bit[1]: clk_start_sel_o 0: clock start after sof 1: clock start after reset bit[0]: sof_sel_o 0: frame start after href starts 1: frame start after sof 0x484c sel_mipi_ctrl4c 0x02 rw bit[7]: debug mode bit[6]: smia fcnt_i select bit[5]: prbs_enable bit[4]: mipi high speed only test mode enable bit[3]: set frame count to inactive mode (keep 0) bit[2:0]: debug mode 0x484d test_patten_data 0xb6 rw data lane test pattern register 0x484e fe_dly 0x10 rw last packet to frame end delay/2 0x484f test_patten_ck_ data 0x55 rw clk_test_patten_reg table 6-19 mipi top registers (sheet 9 of 9) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-31 6.20 temperature monitor [04d00x ~ 0x4d23] 6.21 aec pk [0x3500 ~ 0x352b] table 6-20 temperature monitor registers address register name default value r/w description 0x4d00 tpm_ctrl_00 0x05 rw bit[7:0]: tpm slope[15:8] 0x4d01 tpm_ctrl_01 0x19 rw bit[7:0]: tpm slope[7:0] 0x4d02 tpm_ctrl_02 0xfd rw bit[7:0]: tpm offset[31:24] 0x4d03 tpm_ctrl_03 0xd1 rw bit[7:0]: tpm offset[23:16] 0x4d04 tpm_ctrl_04 0xff rw bit[7:0]: tpm offset[15:8] 0x4d05 tpm_ctrl_05 0xff rw bit[7:0]: tpm offset[7:0] 0x4d06~ 0x4d23 tpm_ctrl ? ? debug registers table 6-21 aec/agc registers (sheet 1 of 5) address register name default value r/w description 0x3500 aec long expo 0x00 rw long exposure bit[7:4]: not used bit[3:0]: long exposure[19:16] 0 x3501 aec long expo 0x02 rw long exposure bit[7:0]: long exposure[15:8] 0x3502 aec long expo 0x00 rw long exposure bit[7:0]: long exposure[7:0] low 4 bits are fraction bits and should be all 0?s color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3503 aec manual 0x00 rw aec manual mode control bit[7]: debug mode bit[6]: digital fraction gain delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[5]: gain change delay option always the same with 0x3503[4] 0: delay 1 frame 1: no delay 1 frame bit[4]: gain delay option 0: delay 1 frame 1: no delay 1 frame bit[3]: not used bit[2]: gain man as sensor gain 0: gain input ({0x3508,0x3509}) as real gain format 1: gain input ({0x3508,0x3509}) as sensor gain format bit[1]: exposure delay option always 0 to make sure otp_dpc catches the correct exposure value 0: delay 1 frame 1: no delay 1 frame bit[0]: exposure change delay option always 0 0: delay 1 frame 1: no delay 1 frame 0x3504~ 0x3506 debug mode ? ? debug mode 0 x3507 aec long gain 0x00 rw long gain bit[7:2]: debug mode bit[1:0]: long gain[17:16] 0x3508 aec long gain 0x00 rw long gain bit[7:0]: long gain[15:8] 0x3509 aec long gain 0x80 rw long gain bit[7:0]: long gain[7:0] low 7 bits are fraction bits 0x350a aec middle expo 0x00 rw middle exposure bit[7:4]: not used bit[3:0]: middle exposure[19:16] table 6-21 aec/agc registers (sheet 2 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-33 0x350b aec middle expo 0x01 rw middle exposure bit[7:0]: middle exposure[15:8] 0x350c aec middle expo 0x00 rw middle exposure bit[7:0]: middle exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x350d aec middle gain 0x00 rw middle gain bit[7:2]: not used bit[1:0]: middle gain[17:16] 0x350e aec middle gain 0x00 rw middle gain bit[7:0]: middle gain[15:8] 0x350f aec middle gain 0x80 rw middle gain bit[7:0]: middle gain[7:0] low 7 bits are fraction bits 0x3510 aec short expo 0x00 rw short exposure bit[7:4]: not used bit[3:0]: short exposure[19:16] 0x3511 aec short expo 0x00 rw short exposure bit[7:0]: short exposure[15:8] 0x3512 aec short expo 0x80 rw short exposure bit[7:0]: short exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x3513 aec short gain 0x00 rw short gain bit[7:2]: not used bit[1:0]: short gain[17:16] 0x3514 aec short gain 0x00 rw short gain bit[7:0]: short gain[15:8] 0x3515 aec short gain 0x80 rw short gain bit[7:0]: short gain[7:0] low 7 bits are fraction bits 0x3516 aec 4 expo 0x00 rw fourth exposure bit[7:4]: not used bit[3:0]: fourth exposure[19:16] 0x3517 aec 4 expo 0x02 rw fourth exposure bit[7:0]: fourth exposure[15:8] 0x3518 aec 4 expo 0x00 rw fourth exposure bit[7:0]: fourth exposure[7:0] low 4 bits are fraction bits and should be all 0?s table 6-21 aec/agc registers (sheet 3 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x3519 aec 4 gain 0x00 rw fourth gain bit[7:2]: not used bit[1:0]: fourth gain[17:16] 0x351a aec 4 gain 0x00 rw fourth gain bit[7:0]: fourth gain[15:8] 0x351b aec 4 gain 0x80 rw fourth gain bit[7:0]: fourth gain[7:0] low 7 bits are fraction bits 0x351c aec 5 expo 0x00 rw fifth exposure bit[7:4]: not used bit[3:0]: fifth exposure[19:16] 0x351d aec 5 expo 0x02 rw fifth exposure bit[7:0]: fifth exposure[15:8] 0x351e aec 5 expo 0x00 rw fifth exposure bit[7:0]: fifth exposure[7:0] low 4 bits are fraction bits and should be all 0?s 0x351f aec 5 gain 0x00 rw fifth gain bit[7:2]: not used bit[1:0]: fifth gain[17:16] 0x3520 aec 5 gain 0x00 rw fifth gain bit[7:0]: fifth gain[15:8] 0x3521 aec 5 gain 0x80 rw fifth gain bit[7:0]: fifth gain[7:0] low 7 bits are fraction bits 0x3522 dig gain frac middle 0x04 rw bit[7]: not used bit[6:0]: middle digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3523 dig gain frac middle 0x00 rw bit[7:0]: middle digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3524 dig gain frac short 0x04 rw bit[7]: not used bit[6:0]: short digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3525 dig gain frac short 0x00 rw bit[7:0]: short digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 4 of 5) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-35 0x3526 dig gain frac 4 0x04 rw bit[7]: not used bit[6:0]: fourth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3527 dig gain frac 4 0x00 rw bit[7:0]: fourth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x3528 dig gain frac 5 0x04 rw bit[7]: not used bit[6:0]: fifth digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x3529 dig gain frac 5 0x00 rw bit[7:0]: fifth digital fraction gain[7:0] valid when 0x3503[2]=1?b1 0x352a dig gain frac long 0x04 rw bit[7]: not used bit[6:0]: long digital fraction gain[14:8] low 11 bits are fraction bits valid when 0x3503[2]=1?b1 0x352b dig gain frac long 0x00 rw bit[7:0]: long digital fraction gain[7:0] valid when 0x3503[2]=1?b1 table 6-21 aec/agc registers (sheet 5 of 5) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.22 blc [0x4000 ~ 0x4033] table 6-22 blc registers (sheet 1 of 4) address register name default value r/w description 0x4000 blc ctrl00 0xf1 rw bit[7]: outrange_trig_en offset out of range trigger function enable signal 0: disable 1: enable bit[6]: format_chg_en format change triggers function enable signal 0: disable 1: enable bit[5]: gain_chg_en gain change triggers function enable signal 0: disable 1: enable bit[4]: exp_chg_en exposure changes trigger function enable signal 0: disable 1: enable bit[3]: manual_trig manually trigger signal rising edge triggers blc bit[2]: freeze_en blc freeze function enable signal when set, blc will freeze offsets will maintain the pre-frame values bit[1]: always_do blc always trigger signal when set, blc triggers every frame unless the freeze_en is enabled bit[0]: debug mode 0x4001~ 0x4002 debug mode ? ? debug mode 0x4003 blc ctrl03 0x14 rw bit[7:0]: black line_num black line number used to calculate the offsets 0x4004 blc ctrl04 0x00 rw bit[7:0]: target[15:8] blc target 0x4005 blc ctrl05 0x40 rw bit[7:0]: target[7:0] blc target in 12-bit domain 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-37 0x4006 blc ctrl06 0x1f rw bit[7:0]: format_chg_fn frame number for format change trigger 0x4007 blc ctrl07 0x1f rw bit[7:0]: reset_trig_fn frame number for reset trigger 0x4008 blc ctrl08 0x01 rw bit[7:0]: manual_trig_fn frame number for manual trigger 0x4009~ 0x400b debug mode ? ? debug mode 0x400c blc ctrl0c 0x00 rw bit[7:0]: offset_trig_thresh[13:6] (works only when register 0x4000[7] = 1) threshold for offset trigger when line_current_offset - blc_line_offset| > offset_trig_thresh, blc update will be set. 0x400d blc ctrl0d 0x20 rw bit[7:2]: offset_trig_thresh[5:0] bit[1:0]: debug mode 0x400e blc ctrl0e 0x00 rw bit[7:0]: bypass_offset[15:8] offset for blc bypass 0x400f blc ctrl0f 0x00 rw bit[7:0]: bypass_offset[7:0] offset for blc bypass 0x4010 debug mode ? ? debug mode 0x4011 blc ctrl11 0x00 rw bit[7:6]: debug mode bit[5]: offset_man_same when it is enabled, the manual offsets will be same. they are all defined by manual_offset00({0x4012,0x4013}) bit[4]: offset_man_en when it is enabled, the offsets will be defined manually with registers manual_offset00 ~ manual_offset11 (0x4012~0x4019) bit[3:1]: debug mode bit[0]: black_line_out_en 0: black line pixels will not be output 1: black line pixels will be output 0x4012 blc ctrl12 0x00 rw bit[7:0]: manual_offset00[15:8] manual offset for normal even-line and even-column pixels 0x4013 blc ctrl13 0x00 rw bit[7:0]: manual_offset00[7:0] table 6-22 blc registers (sheet 2 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x4014 blc ctrl14 0x00 rw bit[7:0]: manual_offset01[15:8] manual offset for normal even-line and odd-column pixels 0x4015 blc ctrl15 0x00 rw bit[7:0]: manual_offset01[7:0] 0x4016 blc ctrl16 0x00 rw bit[7:0]: manual_offset10[15:8] manual offset for normal odd-line and even-column pixels 0x4017 blc ctrl17 0x00 rw bit[7:0]: manual_offset10[7:0] 0x4018 blc ctrl18 0x00 rw bit[7:0]: manual_offset11[15:8] manual offset for normal odd-line and odd-column pixels 0x4019 blc ctrl19 0x00 rw bit[7:0]: manual_offset11[7:0] 0x401a~ 0x401f debug mode ? ? debug mode 0x4020 anchor left start 0x02 rw bit[7:4]: debug mode bit[3:0]: anchor left start[11:8] 0x4021 anchor left start 0x40 rw bit[7:0]: anchor left start[7:0] 0x4022 anchor left end 0x03 rw bit[7:4]: debug mode bit[3:0]: anchor left end[11:8] 0x4023 anchor left end 0x3f rw bit[7:0]: anchor left end[7:0] 0x4024 anchor right start 0x07 rw bit[7:4]: debug mode bit[3:0]: anchor right start[11:8] 0x4025 anchor right start 0xc0 rw bit[7:0]: anchor right start[7:0] 0x4026 anchor right end 0x08 rw bit[7:4]: debug mode bit[3:0]: anchor right end[11:8] 0x4027 anchor right end 0xbf rw bit[7:0]: anchor right end[7:0] 0x4028 top zline st 0x00 rw top zline start 0x4029 top zline num 0x02 rw top zline number 0x402a top blkline st 0x06 rw top blkline start 0x402b top blkline num 0x04 rw top blkline number 0x402c bot zline st 0x02 rw bot zline start table 6-22 blc registers (sheet 3 of 4) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-39 6.23 isp top [0x5000 ~ 0x5033] 0x402d bot zline num 0x02 rw bot zline number 0x402e bot blkline st 0x0e rw bot blkline start 0x402f bot blkline num 0x04 rw bot blkline number 0x4030 dcblc k1 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k1[11:8] 0x4031 dcblc k1 0x00 rw bit[7:0]: dcblc k1[7:0] 0x4032 dcblc k2 0x01 rw bit[7:4]: debug mode bit[3:0]: dcblc k2[11:8] 0x4033 dcblc k2 0x00 rw bit[7:0]: dcblc k2[7:0] table 6-23 isp top registers (sheet 1 of 3) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7]: digital gain enable 0: disable 1: enable bit[6]: bin enable 0: disable 1: enable bit[5]: otp enable 0: disable 1: enable bit[4]: wb gain enable 0: disable 1: enable bit[3:2]: debug mode bit[1]: average enable bit[0]: isp enable table 6-22 blc registers (sheet 4 of 4) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 0x5001 isp ctrl1 0x11 rw bit[7]: new_stg_hdr_en bit[6]: new_stg_eof_en bit[5]: debug mode bit[4]: isp eof select bit[3]: isp sof select bit[2]: debug mode bit[0]: blc 0: disable 1: enable 0x5002 isp ctrl2 0x85 rw bit[7]: isp raw enable 0: disable 1: enable bit[6:4]: debug mode bit[3]: wb bias man enable 0: disable 1: enable bit[2]: wb bias on bit[1]: digital gain bias man enable bit[0]: digital gain bias on 0x5003 isp ctrl03 0x10 rw bias manual 0x5004~ 0x500b debug mode ? ? debug mode 0x500c isp ctrl0c 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb r gain[11:8] 0x500d isp ctrl0d 0x00 rw bit[7:0]: long wb r gain[7:0] 0x500e isp ctrl0e 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb g gain[11:8] 0x500f isp ctrl0f 0x00 rw bit[7:0]: long wb g gain[7:0] 0x5010 isp ctrl10 0x04 rw bit[7:4]: debug mode bit[3:0]: long wb b gain[11:8] 0x5011 isp ctrl11 0x00 rw bit[7:0]: long wb b gain[7:0] 0x5012 isp ctrl 12 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb r gain[11:8] 0x5013 isp ctrl 13 0x00 rw bit[7:0]: middle wb r gain[7:0] 0x5014 isp ctrl 14 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb g gain[11:8] 0x5015 isp ctrl 15 0x00 rw bit[7:0]: middle wb g gain[7:0] 0x5016 isp ctrl 16 0x04 rw bit[7:4]: debug mode bit[3:0]: middle wb b gain[11:8] 0x5017 isp ctrl 17 0x00 rw bit[7:0]: middle wb b gain[7:0] table 6-23 isp top registers (sheet 2 of 3) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-41 0x5018 isp ctrl 18 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb r gain[11:8] 0x5019 isp ctrl 19 0x00 rw bit[7:0]: short wb r gain[7:0] 0x501a isp ctrl 1a 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb g gain[11:8] 0x501b isp ctrl 1b 0x00 rw bit[7:0]: short wb g gain[7:0] 0x501c isp ctrl 1c 0x04 rw bit[7:4]: debug mode bit[3:0]: short wb b gain[11:8] 0x501d isp ctrl 1d 0x00 rw bit[7:0]: short wb b gain[7:0] 0x501e~ 0x5030 debug mode ? ? debug mode 0x5031 isp ctrl 31 0x20 rw bit[5]: bin mode select bit[4]: bypass sof bit[3]: long/short reverse wb gain bit[2]: long/short reverse digital gain bit[1:0]: debug mode 0x5032~ 0x5033 debug mode ? ? debug mode table 6-23 isp top registers (sheet 3 of 3) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.24 pre_isp control [0x5040 ~ 0x506c] table 6-24 pre_isp control registers address register name default value r/w description 0x5040 pre isp test ctrl 0x 00 rw bit[7]: test_enable bit[6]: rolling enable rolling bar in test mode bit[5]: transparent image + normal image enable bit[4]: square black white enable bit[3:2]: color_bar style 00: horizontal bar 01: vertical bar 10: horizontal fading bar 11: vertical fading bar bit[1:0]: test selection 00: color bar 01: random data 10: square black white 11: black 0x5041 pre isp win 0x41 rw bit[7]: not used bit[6]: window cut enable bit[5]: isp test, low bits to 0 bit[4]: random, random data reset bit[3:0]: random seed 0x5042~ 0x5047 debug mode ? ? debug mode 0x5048 pre isp x off 0x00 rw bit[7:0]: x manual offset[15:8] 0x5049 pre isp x off 0x00 rw bit[7:0]: x manual offset[7:0] 0x504a pre isp y off 0x00 rw bit[7:0]: y manual offset15:8] 0x504b pre isp y off 0x00 rw bit[7:0]: y manual offset[7:0] 0x504c~ 0x506c debug mode ? ? debug mode 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-43 6.25 binning control [0x5301 ~ 0x530f] table 6-25 binning control registers (sheet 1 of 2) address register name default value r/w description 0x5301 bin ctrl 01 0x 00 rw bit[7:5]: debug mode bit[4]: enable manual input filter coefficients bit[3:0]: debug mode 0x5302 bin ctrl 02 0x23 rw bit[7:6]: debug mode bit[5:4]: first row number of output bg rows bit[3]: debug mode bit[2:0]: first row number of output gr rows 0x5303 bin ctrl 03 0x22 rw bit[7]: debug mode bit[6:4]: step between two output rows bit[3]: debug mode bit[2:0]: shift number of row calculation 0x5304 bin ctrl 04 0x40 rw bit[7:4]: b row filter coefficient 0 bit[3]: debug mode bit[2:0]: b row filter coefficient 1 0x5305 bin ctrl 05 0x31 rw bit[7:4]: r row filter coefficient 0 bit[3]: debug mode bit[2:0]: r row filter coefficient 1 0x5306 bin ctrl 06 0x23 rw bit[7:6]: debug mode bit[5:4]: first column number of output b columns bit[3]: debug mode bit[2:0]: first column number of output r columns 0x5307 bin ctrl 07 0x54 rw bit[7]: enable column filter with two coefficients bit[6:4]: shift number of column calculation bit[3:0]: step between two output columns 0x5308 bin ctrl 08 0x03 rw bit[7:3]: debug mode bit[2:0]: b column filter coefficient 0[2:0] 0x5309 bin ctrl 09 0x19 rw bit[7:0]: b column filter coefficient 1[7:0] 0x530a bin ctrl 0a 0x09 rw bit[7]: debug mode bit[6:0]: b column filter coefficient 2[6:0] 0x530b bin ctrl 0b 0x01 rw bit[7:4]: debug mode bit[3:0]: b column filter coefficient 3[3:0] 0x530c bin ctrl 0c 0x01 rw bit[7:3]: debug mode bit[2:0]: r column filter coefficient 0[2:0] 0x530d bin ctrl 0d 0x09 rw bit[7:0]: r column filter coefficient 1[7:0] color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.26 otp_dpc control [0x5000 ~ 0x552a] 0x530e bin ctrl 0e 0x19 rw bit[7]: debug mode bit[6:0]: r column filter coefficient 2[6:0] 0x530f bin ctrl 0f 0x03 rw bit[7:4]: debug mode bit[3:0]: r column filter coefficient 3[3:0] table 6-26 otp_dpc control registers (sheet 1 of 2) address register name default value r/w description 0x5000 isp ctrl0 0xf3 rw bit[7:6]: debug mode bit[5]: otp enable 0: disable 1: enable 0x5500 otp dpc start 0x00 rw bit[7:1]: debug mode bit[0]: otp start address[8] 0x5501 otp dpc start 0x00 rw bit[7:0]: otp start address[7:0] 0x5502 otp dpc end 0x01 rw bit[7:1]: debug mode bit[0]: otp end address[8] 0x5503 otp dpc end 0xff rw bit[7:0]: otp end address[7:0] 0x5505 otp dpc ctrl 05 0x6c rw bit[7]: debug mode bit[6:5]: recover method select 00: left 1 neighbor pixel on same channel 01: minimum of left 2 neighbor pixels 10: maximum of left and right 1 neighbor pixels 11: maximum between the minimum of left 2 neighbor pixels and the minimum of right 2 neighbor pixels bit[4]: recover with fixed pattern bit[3]: fixed pattern mode 0: 0x00 1: 0xff bit[1]: sensor expos ure constrain enable bit[0]: sensor gain constrain enable table 6-25 binning control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-45 6.27 windowing (win) control [0x5980 ~ 0x598c] 0x5506 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[15:8] 0 x5507 otp dpc expo constraint l 0x00 rw bit[7:0]: otp expos ure constrain long[7:0] 0x5508 otp dpc gain constraint l 0x07 rw otp gain constrain long 0x5509 otp dpc thre l 0x08 rw otp threshold long 0x5524 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[15:8] 0x5525 otp expo constrain m 0x00 rw bit[7:0]: otp exposure constrain middle[7:0] 0x5526 otp gain constrain m 0x07 rw otp gain constrain middle 0x5527 otp thre ms 0x88 rw bit[7:4]: otp threshold middle bit[3:0]: otp threshold short 0x5528 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[15:8] 0x5529 otp expo constrain s 0x00 rw bit[7:0]: otp expos ure constrain short[7:0] 0x552a otp gain constrain s 0x07 rw otp gain constrain short table 6-27 win control registers (sheet 1 of 2) address register name default value r/w description 0x5980 win xstart_off 0x00 rw bit[7:5]: debug mode bit[4:0]: x start offset[12:8] 0x5981 win xstart_off 0x00 rw bit[7:0]: x start offset[7:0] 0x5982 win ystart_off 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] 0x5983 win ystart_off 0x00 rw bit[7:0]: y start offset[7:0] 0x5984 win width 0x0a rw bit[7:5]: debug mode bit[4:0]: window width[12:8] table 6-26 otp_dpc control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 6.28 average (avg) control [0x5680 ~ 0x5693] 0x5985 win width 0x80 rw bit[7:0]: window width[7:0] 0x5986 win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] 0x5987 win height 0xf0 rw bit[7:0]: window height[7:0] 0x5988 win man 0x00 rw bit[7:1]: debug mode bit[0]: window size manual 0: disable 1: enable 0x5989~ 0x598c debug mode ? ? debug mode table 6-28 avg control registers (sheet 1 of 2) address register name default value r/w description 0x5680 avg x start 0x00 rw bit[7:4]: debug mode bit[3:0]: x start offset[11:8] valid when 0x5690[0]=1 0x5681 avg x start 0x00 rw bit[7:0]: x start offset[7:0] valid when 0x5690[0]=1 0x5682 avg y start 0x00 rw bit[7:4]: debug mode bit[3:0]: y start offset[11:8] valid when 0x5690[0]=1 0x5683 avg y start 0x00 rw bit[7:0]: y start offset[7:0] valid when 0x5690[0]=1 0x5684 avg win width 0x0a rw bit[7:4]: debug mode bit[3:0]: window width[11:8] valid when 0x5690[0]=1 0x5685 avg win width 0x80 rw bit[7:0]: window width[7:0] valid when 0x5690[0]=1 0x5686 avg win height 0x05 rw bit[7:4]: debug mode bit[3:0]: window height[11:8] valid when 0x5690[0]=1 0 x5687 avg win height 0xf0 rw bit[7:0]: window height[7:0] valid when 0x5690[0]=1 table 6-27 win control registers (sheet 2 of 2) address register name default value r/w description 10.23.2013 preliminary specification propr ietary to omnivision technologies 6-47 0x5688 avg wt 0 0x11 rw bit[7:4]: weight of zone 01 bit[3:0]: weight of zone 00 0x5689 avg wt 1 0x11 rw bit[7:4]: weight of zone 03 bit[3:0]: weight of zone 02 0x568a avg wt 2 0x11 rw bit[7:4]: weight of zone 11 bit[3:0]: weight of zone 10 0x568b avg wt 3 0x11 rw bit[7:4]: weight of zone 13 bit[3:0]: weight of zone 12 0x568c avg wt 4 0x11 rw bit[7:4]: weight of zone 21 bit[3:0]: weight of zone 20 0x568d avg wt 5 0x11 rw bit[7:4]: weight of zone 23 bit[3:0]: weight of zone 22 0x568e avg wt 6 0x11 rw bit[7:4]: weight of zone 31 bit[3:0]: weight of zone 30 0x568f avg wt 7 0x11 rw bit[7:4]: weight of zone 33 bit[3:0]: weight of zone 32 0x5690 avg manual ctrl 0x02 rw bit[7:2]: debug mode bit[1]: average option 0: sum = (4b+9g2+10r)/8 1: sum = b+g2+r bit[0]: average size manual 0: disable 1: enable 0x5691 avg wt sum readout ? r bit[7:0]: average weight sum 0x5692 avg sccb done ? r average calculated indicating signal for sccb read 0x5693 avg readout ? r bit[7:0]: high 8-bit of average output table 6-28 avg control registers (sheet 2 of 2) address register name default value r/w description color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-1 7 operating specifications 7.1 absolute maximum ratings 7.2 functional temperature table 7-1 absolute maximum ratings parameter absolute maximum rating a a. exceeding the absolute maximum ratings shown above inva lidates all ac and dc electric al specifications and may result in permanent damage to the device. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. ambient storage temperature -40c to +125c supply voltage (with respect to ground) v dd-a 4.5v v dd-d 3v v dd-io 4.5v electro-static discharge (esd) human body model 2000v machine model 200v all input/output voltages (with respect to ground) -0.3v to v dd-io + 1v i/o current on any input or output pin 200 ma peak solder temperature (10 second dwell time) 245c table 7-2 functional temperature parameter range operating temperature (for applications up to 90fps) a a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range -30c to +85c junction temperature stable image temperature b b. image quality remains stable throughout this temperature range 0c to +60c junction temperature color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 7.3 dc characteristics table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit supply v dd-a supply voltage (analog) 2.6 2.8 3.0 v v dd-io supply voltage (digital i/o) 1.7 1.8 3.0 v v dd-d supply voltage (digital core for 4-lane mipi up to 1000 mbps/lane) 1.1 1.2 1.3 v i dd-a active (operating) current b 40 45 ma i dd-io 37 ma i dd-d 120 150 ma i dds-sccb--a standby (sccb) current c 10 20 a i dds-sccb--io 50 70 a i dds-sccb--d 120 ma i dds-pwdnb-a standby (pwdnb) current c 10 20 a i dds-pwdnb-io 20 30 a i dds-pwdnb-d 0.2 20 ma i dds-xshutdown-a standby (xshutdown) current c 0.3 2 a i dds-xshutdown-io 0.3 2 a i dds-xshutdown-d 28 a digital inputs (typical conditions: avdd = 2.8v, dvdd = 1.2v, dovdd = 1.8v) v il input voltage low v dd-io 0.3 v v ih input voltage high v dd-io 0.7 v c in input capacitor 10 pf digital outputs (standard loading 25 pf) v oh output voltage high v dd-io 0.9 v v ol output voltage low v dd-io 0.1 v 10.23.2013 preliminary specification propr ietary to omnivision technologies 7-3 7.4 timing characteristics serial interface inputs v il d sioc and siod -0.5 0 0.54 v v ih sioc and siod 1.28 1.8 3.0 v a. maximum active current is m easured under typical supply voltage b. dvdd is provided by external regulator for lower power consumption. dvdd and evdd are tied together. dovdd = 1.8v c. standby current is measured at room temperature with external clock off d. based on dovdd = 1.8v table 7-4 timing characteristics symbol parameter min typ max unit oscillator and clock input f osc frequency (extclk) a a. for input clock range 6~64mhz, the OV4689 can tole rate input clock period jitter up to 600ps peak-to-peak 62464 mhz t r , t f clock input rise/fall time (see footnote b ) b. for clock input rise/fall time, max is 27% of whole clock period ns clock input duty cycle 45 50 55 % table 7-3 dc characteristics (-30c < t j < 85c) symbol parameter min typ max a unit color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies 8-1 8 mechanical specifications 8.1 physical specifications figure 8-1 package specifications table 8-1 package dimensions parameter symbol min typ max unit package body dimension x a 6605 6630 6655 m package body dimension y b 5805 5830 5855 m package height c 680 740 800 m ball height c1 100 130 160 m package body thickness c2 575 610 645 m thickness from top glass surface to wafer c3 425 445 465 m glass thickness c4 385 400 415 m air gap between sensor and glass c5 41 45 49 m ball diameter d 220 250 280 m total ball count n 67 (7 nc) pins pitch x-axis j1 710 m pins pitch y-axis j2 580 m edge-to-pin center distance along x s1 465 475 505 m edge-to-pin center distance along y s2 585 595 625 m a top view (bumps down) a b c d e f g h j b 1 2 3 4 5 6 7 8 9 a b c d e f g h j d center of bga (die) = center of the package j1 s1 bottom view (bumps up) note 1 part marking code: w - ovt product version x - year part was assembled y - month part was assembled z - wafer number abcd - last four digits of lot number 5 4 3 2 168 79 c side view c1 c2 s2 j2 c3 c4 c5 x wyz b acd 4689_csp5_ds_8_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 8.2 ir reflow specifications figure 8-2 ir reflow ramp rate requirements note the OV4689 uses a lead-free package. table 8-2 reflow conditions ab a. maximum number of reflow cycles =3 b. n2 gas reflow or control o2 gas ppm<500 as recommendation zone description exposure ramp up a (t 0 to t min ) heating from room temperature to 150c temperature slope 3c per second soaking heating from 150c to 200c 90 ~ 150 seconds ramp up b (t l to t p ) heating from 217c to 245c temperature slope 3c per second peak temperature maximum temperature in smt 245c +0/-5c (duration max 30sec) reflow (t l to t l ) temperature higher than 217c 30 ~ 120 seconds ramp down a (t p to t l ) cooling down from 245c to 217c temperature slope 3c per second ramp down b (t l to t f ) cooling down from 217c to room temperature temperature slope 2c per second t 0 to t p room temperature to peak temperature 8 minutes time (sec) soaking reflow cooling temperature (c) 0 20 40 60 80 100 120 140 160 180 200 520 480 440 400 360 320 280 500 460 420 380 340 300 260 240 220 540 0.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 ramp up 4689_csp5_ds_8_2 t l t max t min t 0 t p t l t f 10.23.2013 preliminary specification propr ietary to omnivision technologies 9-1 9 optical specifications 9.1 sensor array center figure 9-1 sensor array center a1 a2 a3 a4 a5 a6 a7 a8 a9 package center (0 m, 0 m) array center (-110 m, -230 m) OV4689 sensor array note 1 note 2 this drawing is not to scale and is for reference only. as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. top view 5440 m 3072 m first pixel readout (-2830 m, 1306 m) 4689_csp5_ds_9_1 color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 10.23.2013 preliminary specification propr ietary to omnivision technologies rev-1 revision history version 1.0 04.18.2013 ? initial release version 1.1 07.25.2013 ? changed title of figure 4-8 to "staggered hdr with virtual channel" ? added figure 4-9, staggered hdr without virtual channel version 1.2 09.18.2013 ? in table 5-1, added bit description for 0x5001[7] and 0x5001[6] ? in table 6-7, added descripti ons for registers 0x3760~0x3764 ? in table 6-23, changed description for 0x5001[7] from debug mode to new_stg_hdr_en and changed description for 0x5001[6] from debug mode to new_stg_eof_en version 1.3 10.23.2013 ? in table 2-5, removed row for t10 ? in figure 2-3 and figure 2-4, removed note and t10 measurement ? in chapter 2, removed section 2.6.2.1 and section 2.6.2.2 ? in table 6-21, changed description of regist er bits 0x3522[7:1], 0x3524[7:1], 0x3526[7:1], 0x3528[7:1], and 0x352a[7:1] to bit[7]: not used ? in table 7-3, changed symbols for standby (sccb) current to i dds-sccb-a , i dds-sccb-io , and i dds-sccb-d ? in table 7-3, changed symbols fo r standby (pwdnb) current to i dds-pwdnb-a , i dds-pwdnb-io , and i dds-pwdnb-d ? in table 7-3, changed symbols for standby (xshutdown) current to i dds-xshutdown-a , i dds-xshutdown-io , and i dds-xshutdown-d color cmos 4 megapixel (2688 x 1520) ima ge sensor with omnibsi-2? technology OV4689 proprietary to omnivision technologies preliminary specification version 1.3 defining the future of digital imaging? website: www.ovt.com omnivision technologies, inc. united states 4275 burton drive santa clara, ca 95054 tel: + 1 408 567 3000 fax: + 1 408 567 3001 email: salesamerican@ovt.com united kingdom hampshire + 44 1256 744 610 germany munich +49 89 63 81 99 88 india bangalore +91 988 008 0140 china beijing + 86 10 6580 1690 shanghai + 86 21 6175 9888 shenzhen + 86 755 8384 9733 hong kong + 852 2403 4011 japan yokohama +81 45 478 7977 osaka +81 6 4964 2606 korea seoul + 82 2 3478 2812 singapore +65 6220 1335 taiwan taipei +886 2 2657 9800 hsinchu +886 3 6110933 |
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